參數(shù)資料
型號: LPC2210FBD144
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: 16-32-bit ARM microcontrollers; flashless, with 10-bit ADC and external memory interface
中文描述: 16/32位的ARM微控制器;閃存less,10位ADC和外部存儲器接口
封裝: LPC2210FBD144/01<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;LPC2220FBD144<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.
文件頁數(shù): 25/50頁
文件大?。?/td> 259K
代理商: LPC2210FBD144
LPC2210_2220_6
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2008
25 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
2
C-bus may be used for test and diagnostic purposes.
6.14 SPI serial I/O controller
The LPC2210/2220 each contain two SPIs. The SPI is a full duplex serial interface,
designed to be able to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends a byte of data to the slave, and
the slave always sends a byte of data to the master.
6.14.1
Features
Compliant with SPI specification.
Synchronous, serial, full duplex, communication.
Combined SPI master and slave.
Maximum data bit rate of one eighth of the input clock rate.
6.15 SSP controller
This peripheral is available in LPC2210/01 and LPC2220 only.
6.15.1
Features
Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National
Semiconductor’s Microwire buses.
Synchronous serial communication.
Master or slave operation.
8-frame FIFOs for both transmit and receive.
4 bits to 16 bits per frame.
6.15.2
Description
The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. Data transfers are in
principle full duplex, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master.
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