參數(shù)資料
型號(hào)： LPC2106FHN48/01,55
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 4/41頁(yè)
文件大?。?/td> 0K
描述： IC ARM7 MCU FLASH 128K 48-HVQFN
標(biāo)準(zhǔn)包裝： 260
系列： LPC2100
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 60MHz
連通性： I²C，Microwire，SPI，SSI，SSP，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 128KB（128K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 3.6 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-VFQFN 裸露焊盤
包裝： 管件
產(chǎn)品目錄頁(yè)面： 704 (CN2011-ZH PDF)
配用： 568-4310-ND - EVAL BOARD LPC2158 W/LCD
568-4297-ND - BOARD EVAL LPC21XX MCB2100
622-1019-ND - BOARD FOR LPC2106 48-LQFP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1005-ND - USB IN-CIRCUIT PROG ARM7 LPC2K
568-1756-ND - BOARD EVAL FOR LPC210X ARM MCU
其它名稱： 568-4368
935286613551
LPC2106FHN48/01-S
LPC2104_2105_2106_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 20 June 2008
12 of 41
NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
6.5 Interrupt controller
The Vectored Interrupt Controller (VIC) accepts all of the Interrupt Request (IRQ) inputs
and categorizes, them as FIQ, vectored IRQ, and non-vectored IRQ as dened by
programmable settings. The programmable assignment scheme means that priorities of
interrupts from the various peripherals can be dynamically assigned and adjusted.
Fast Interrupt reQuest (FIQ) has the highest priority. If more than one request is assigned
to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor.
The fastest possible FIQ latency is achieved when only one request is classied as FIQ,
because then the FIQ service routine can simply start dealing with that device. But if more
than one request is assigned to the FIQ class, the FIQ service routine can read a word
from the VIC that identies which FIQ source(s) is (are) requesting an interrupt.
Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned
to this category. Any of the interrupt requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to produce
the IRQ signal to the ARM processor. The IRQ service routine can start by reading a
register from the VIC and jumping there. If any of the vectored IRQs are requesting, the
VIC provides the address of the highest-priority requesting IRQs service routine,
otherwise it provides the address of a default routine that is shared by all the non-vectored
IRQs. The default routine can read another VIC register to see what IRQs are active.
6.5.1 Interrupt sources
Table 4 lists the interrupt sources for each peripheral function. Each peripheral device has
one interrupt line connected to the Vectored Interrupt Controller, but may have several
internal interrupt ags. Individual interrupt ags may also represent more than one
interrupt source.
Table 4.
Interrupt sources
Block
Flag(s)
VIC channel #
WDT
Watchdog Interrupt (WDINT)
0
-
Reserved for software interrupts only
1
ARM Core
EmbeddedICE, DbgCommRx
2
ARM Core
EmbeddedICE, DbgCommTx
3
Timer 0
Match 0 to 3 (MR0, MR1, MR2, MR3)
Capture 0 to 2 (CR0, CR1, CR2)
4
Timer 1
Match 0 to 3 (MR0, MR1, MR2, MR3)
Capture 0 to 3 (CR0, CR1, CR2, CR3)
5
UART 0
Rx Line Status (RLS)
Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Auto-Baud Time-Out (ABTO)[1]
End of Auto-Baud (ABEO)[1]
6
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