參數(shù)資料
型號(hào): LPC2106FHN48/01,55
廠商: NXP Semiconductors
文件頁(yè)數(shù): 34/41頁(yè)
文件大?。?/td> 0K
描述: IC ARM7 MCU FLASH 128K 48-HVQFN
標(biāo)準(zhǔn)包裝: 260
系列: LPC2100
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 60MHz
連通性: I²C,Microwire,SPI,SSI,SSP,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 128KB(128K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-VFQFN 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁(yè)面: 704 (CN2011-ZH PDF)
配用: 568-4310-ND - EVAL BOARD LPC2158 W/LCD
568-4297-ND - BOARD EVAL LPC21XX MCB2100
622-1019-ND - BOARD FOR LPC2106 48-LQFP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1005-ND - USB IN-CIRCUIT PROG ARM7 LPC2K
568-1756-ND - BOARD EVAL FOR LPC210X ARM MCU
其它名稱: 568-4368
935286613551
LPC2106FHN48/01-S
LPC2104_2105_2106_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 20 June 2008
4 of 41
NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
4.
Block diagram
(1) Shared with GPIO.
(2) When test/debug interface is used, GPIO/other functions sharing these pins are not available.
(3) Available on LPC2104/2105/2106/01 only.
Fig 1.
Block diagram
SCL(1)
P0[31:0]
TRST(2)
TMS(2)
TCK(2)
TDI(2)
TDO(2)
XTAL2
XTAL1
EINT[2:0](1)
AHB BRIDGE
PLL
PWM0
ARM7TDMI-S
LPC2104/2105/2106
RESET
CAP0[2:0](1)
CAP1[3:0](1)
MAT0[2:0](1)
MAT1[3:0](1)
SDA(1)
RXD[1:0](1)
TXD[1:0](1)
DSR1(1), CTS1(1),
RTS1(1), DTR1(1),
DCD1(1), RI1(1)
RTCK
ARM7 LOCAL BUS
INTERNAL
SRAM
CONTROLLER
INTERNAL
FLASH
CONTROLLER
16/32/64 kB
SRAM
128 kB
FLASH
EXTERNAL
INTERRUPTS
CAPTURE/
COMPARE
TIMER 0/TIMER 1
GENERAL
PURPOSE I/O
TEST/DEBUG
INTERFACE
EMULA
TION
TRA
CE
MODULE
AMBA Advanced High-performance
Bus (AHB)
system
clock
SYSTEM
FUNCTIONS
VECTORED
INTERRUPT
CONTROLLER
AHB
DECODER
I2C-BUS SERIAL
INTERFACE
AHB TO APB
BRIDGE
APB
DIVIDER
Advanced Peripheral
Bus (APB)
UART0/UART1
WATCHDOG
TIMER
SYSTEM
CONTROL
REAL-TIME CLOCK
002aaa412
VDD(3V3)
VSS
VDD(1V8)
PWM[6:1](1)
P0
HIGH-SPEED
GPIO(3)
32 PINS TOTAL
SCK(1)
MOSI(1)
MISO(1)
SSEL(1)
SPI/SSP(3)
SERIAL INTERFACE
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