參數(shù)資料
型號: LPC1317FBD64,551
廠商: NXP Semiconductors
文件頁數(shù): 52/77頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 64KB FLASH 64LQFP
標準包裝: 160
系列: LPC13xx
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 72MHz
連通性: I²C,Microwire,SPI,SSI,SSP,UART/USART
外圍設備: 欠壓檢測/復位,POR,WDT
輸入/輸出數(shù): 51
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 4K x 8
RAM 容量: 10K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-LQFP
包裝: 托盤
其它名稱: 568-9596
LPC1315_16_17_45_46_47
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 20 September 2012
56 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
10.6 SSP interface
[1]
Tcy(clk) = (SSPCLKDIV (1 + SCR) CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
[2]
Tamb = 40 C to 85 C.
[3]
Tcy(clk) = 12 Tcy(PCLK).
[4]
Tamb = 25 C; VDD = 3.3 V.
Table 16.
Dynamic characteristics: SSP pins in SPI mode
Symbol
Parameter
Conditions
Min
Max
Unit
SSP master
Tcy(clk)
clock cycle time
full-duplex mode
40
-
ns
when only transmitting [1]
27.8
-
ns
tDS
data set-up time
in SPI mode;
2.4 V
V
DD 3.6 V
15
-
ns
2.0 V
V
DD < 2.4 V
20
-
ns
tDH
data hold time
in SPI mode
0-
ns
tv(Q)
data output valid time
in SPI mode
-10
ns
th(Q)
data output hold time
in SPI mode
0-
ns
SSP slave
Tcy(PCLK)
PCLK cycle time
13.9
-
ns
tDS
data set-up time
in SPI mode
0-
ns
tDH
data hold time
in SPI mode
3
T
cy(PCLK) + 4
-
ns
tv(Q)
data output valid time
in SPI mode
-3
T
cy(PCLK) + 11
ns
th(Q)
data output hold time
in SPI mode
-2
T
cy(PCLK) + 5
ns
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