參數(shù)資料
型號(hào)： LPC11C12FBD48
廠商： NXP Semiconductors N.V.
元件分類： 32位微控制器
英文描述： Cortex-M0 with 16 kB flash, 8 kB SRAM, CAN and CANopen drivers on-chip
中文描述： Cortex-M0,16KB閃存，8 KB靜態(tài)隨機(jī)存儲(chǔ)器，CAN和CANopen片上驅(qū)動(dòng)
封裝： LPC11C12FBD48/301<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;
文件頁(yè)數(shù)： 47/62頁(yè)
文件大?。?/td> 487K
代理商： LPC11C12FBD48
LPC11CX2_CX4
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 27 June 2011
47 of 62
NXP Semiconductors
LPC11Cx2/Cx4
32-bit ARM Cortex-M0 microcontroller
[6]
The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA
output stage t
f
is specified at 250 ns. This allows series protection resistors to be connected in between the
SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t
f
.
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors
are used, designers should allow for this when considering bus timing.
[7]
[8]
The maximum t
HD;DAT
could be 3.45
s and 0.9
s for Standard-mode and Fast-mode but must be less than
the maximum of t
VD;DAT
or t
VD;ACK
by a transition time (see
UM10204
). This maximum must only be met if
the device does not stretch the LOW period (t
LOW
) of the SCL signal. If the clock stretches the SCL, the
data must be valid by the set-up time before it releases the clock.
[9]
tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in
transmission and the acknowledge.
[10] A Fast-mode I
2
C-bus device can be used in a Standard-mode I
2
C-bus system but the requirement t
SU;DAT
=
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period
of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line t
r(max)
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard-mode I
2
C-bus
specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
10.6 SPI interfaces
Fig 20. I
2
C-bus pins clock timing
002aaf425
t
f
70 %
30 %
SDA
t
f
70 %
30 %
S
70 %
30 %
70 %
30 %
t
HD;DAT
SCL
1 / f
SCL
70 %
30 %
70 %
30 %
t
VD;DAT
t
HIGH
t
LOW
t
SU;DAT
Table 18.
Symbol
SPI master (in SPI mode)
T
cy(clk)
clock cycle time
Dynamic characteristics of SPI pins in SPI mode
Parameter
Conditions
Min
Typ
Max
Unit
full-duplex mode
when only transmitting
in SPI mode
2.4 V
V
DD
3.6 V
2.0 V
V
DD
< 2.4 V
1.8 V
V
DD
< 2.0 V
in SPI mode
[1]
50
40
15
-
-
ns
ns
ns
[1]
t
DS
data set-up time
[2]
-
-
[2]
20
24
0
-
0
ns
ns
ns
ns
ns
[2]
-
-
-
-
-
-
10
-
t
DH
t
v(Q)
t
h(Q)
SPI slave (in SPI mode)
T
cy(PCLK)
PCLK cycle time
data hold time
data output valid time in SPI mode
data output hold time in SPI mode
[2]
[2]
[2]
20
-
-
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LPC11C12FBD48/301 功能描述:ARM微控制器 - MCU 32-bit Cortex M0 16KB 8K RAM CAN RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT
LPC11C12FBD48/301, 功能描述:ARM微控制器 - MCU 32b 16K Flash 40I/O RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT
LPC11C12FBD48/301,15 制造商:NXP Semiconductors 功能描述:Bulk
LPC11C12FBD48-301 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB SRAM; C_CAN
LPC11C14FB301 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB SRAM C_CAN
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