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參數資料
| 型號： | LMX2542LQX2121 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum Cellular and GPS Frequency Synthesizer System with Integrated VCO |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, QCC28 |
| 封裝： | 5 X 5 MM, 0.75 MM HEIGHT, LLP-28 |
| 文件頁數： | 3/22頁 |
| 文件大?。?/td> | 253K |
| 代理商： | LMX2542LQX2121 |
Connection Diagram
Leadless Leadframe Package (LQ)
(Top View)
20082402
Note:
Analog GND connected through exposed die attached pad.
Pin Description
Pin No.
1
2
Pin Name
Fin
V
CC
I/O
I
—
Description
IF PLL buffer/prescaler input. Small signal input from the VCO.
Power supply bias for the IF PLL analog circuits. V
CC
may range from 2.7V to 3.3V.
Bypass capacitors should be placed as close as possible to this pin and be connected
directly to the ground plane on the printed circuit board.
IF PLL charge pump output. The output is connected to the external loop filter, which
drives the input of the IF VCO.
No Connect. Do not connect to any node on the printed circuit board.
MICROWIRE Latch Enable Input. High impedance CMOS input. When LE transitions
from LOW to HIGH, DATA stored in the shift register is loaded into one of 6 internal
control registers.
MICROWIRE Clock Input. High impedance CMOS input. DATA is clocked into the 24-bit
shift register on the rising edge of CLK.
MICROWIRE Data Input. High impedance CMOS input. Binary serial data. The MSB of
DATA is shifted in first.
Power supply bias for the RF VCO. V
DD
may range from 2.7V to 3.3V. Bypass
capacitors should be placed as close as possible to this pin and be connected directly
to the ground plane on the printed circuit board.
No Connect. Do not connect to any node on the printed circuit board.
No Connect. Do not connect to any node on the printed circuit board.
No Connect. Do not connect to any node on the printed circuit board.
No Connect. Do not connect to any node on the printed circuit board.
Power supply bias for the RF VCO. V
DD
may range from 2.7V to 3.3V. Bypass
capacitors should be placed as close as possible to this pin and be connected directly
to the ground plane on the printed circuit board.
Power supply bias for the RF VCO output buffer. V
DD
may range from 2.7V to 3.3V.
Bypass capacitors should be placed as close as possible to this pin and be connected
directly to the ground plane on the printed circuit board.
Buffered RF VCO output.
Power supply bias for the RF PLL prescaler. V
CC
may range from 2.7V to 3.3V. Bypass
capacitors should be placed as close as possible to this pin and be connected directly
to the ground plane on the printed circuit board.
3
CPout
O
4
5
NC
LE
—
I
6
CLK
I
7
DATA
I
8
V
DD
—
9
10
11
12
13
NC
NC
NC
NC
V
DD
—
—
—
—
—
14
V
DD
—
15
16
RFout
V
CC
O
—
L
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| LMX2571EVM | 功能描述:LMX2571 PLLatinum? Series Timing, Frequency Synthesizer Evaluation Board 制造商:texas instruments 系列:PLLatinum?? 零件狀態(tài):有效 主要用途:計時，頻率合成器 嵌入式:- 使用的 IC/零件:LMX2571 主要屬性:帶 VCO 的單路分數-N PLL 輔助屬性:SMA 連接器 所含物品:板 標準包裝:1 |
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| LMX2581 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:LMX2581 Wideband Frequency Synthesizer with Integrated VCO |
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