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參數(shù)資料
| 型號(hào)： | LMX2542LQX2121 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum Cellular and GPS Frequency Synthesizer System with Integrated VCO |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, QCC28 |
| 封裝： | 5 X 5 MM, 0.75 MM HEIGHT, LLP-28 |
| 文件頁數(shù)： | 11/22頁 |
| 文件大小： | 253K |
| 代理商： | LMX2542LQX2121 |
1.0 Functional Description
LMX2542 is a highly integrated, high performance, low
power, frequency synthesizer system optimized for Cellular-
CDMA 1xRTT and IS-95 mobile handsets and data systems
with GPS capabilities. Using a proprietary digital phase
locked loop technique, LMX2542 generates very stable, low
noise local oscillator (LO) signals for up and down conver-
sion in wireless communications devices.
LMX2542 includes a Voltage Controlled Oscillator (VCO) for
the Cellular-CDMA and GPS frequency bands, a loop filter,
and a Fractional-N RF PLL based on a
Σ
modulator which
supports frequency resolutions as low as 5 kHz. In concert,
these blocks form a closed loop RF synthesizer system. The
RF synthesizer system operates from 2087.73 MHz to
2155.14 MHz. The need for external components is limited
to a few passive elements for matching the RF output im-
pedance, and bypass elements for power line stabilization.
The Fractional-N RF PLL (
Σ
modulator architecture) deliv-
ers low spurious thus providing a significant improvement
over other PLL solutions. In addition, the Fractional-N RF
PLL facilitates faster lock times, which reduces power con-
sumption and system set-up time. Furthermore, the RF loop
filter occupies a much smaller area as opposed to the
Integer-N architecture. This allows the RF loop filter to be
embedded into the circuit, thus minimizing the external noise
coupling.
LMX2542 includes an Integer-N IF PLL also. For more flex-
ible loop filter designs, the IF PLL includes a 4-level pro-
grammable charge pump. Together with an external VCO
and loop filter, LMX2542 makes a complete closed loop IF
synthesizer system. The default IF frequency is 367.20 MHz.
The circuit also supports commonly used reference oscillator
frequencies of 19.20 MHz and 19.68 MHz.
1.1 FREQUENCY GENERATION
1.1.1 RF Frequency Selection
The RF synthesizer (Cellular-CDMA) divide ratio can be
calculated using the following equation:
20082407
where:
RF_A
<
RF_B
f
RFout
:
f
OSCin
:
RF_A :
RF VCO output frequency
Reference oscillator frequency
Preset divide ratio of the RF PLL
binary 3-bit swallow counter
(0
≤
RF_A
≤
7)
RF_B :
Preset divide ratio of the RF PLL
binary 4-bit programmable counter
(2
≤
RF_B
≤
15)
Preset numerator of the RF PLL
binary 11-bit modulus counter
(0
≤
RF_FN
<
1920 for f
OSCin
=
19.20 MHz)
(0
≤
RF_FN
<
1968 for f
OSCin
=
19.68 MHz)
RF_FN :
Note:
When the FREQ_OFF bit is set to 1, frequencies with
5 kHz resolution can be generated. In the same way outlined
above, the divide ratio for the desired frequency less 5 kHz
should be programmed. When the FREQ_OFF bit (R1[2]) is
set to 1, the programmed frequency will be shifted by +5 kHz
in order to achieve the desired frequency. Refer to
Section
2.3.1
for details on how to program the FREQ_OFF bit.
1.1.2 IF Frequency Selection
The IF synthesizer divide ratio can be calculated using the
following equation:
20082409
where:
IF_A
<
IF_B
f
Fin
:
f
OSCin
:
IF_A :
IF VCO output frequency
Reference oscillator frequency
Preset divide ratio of the IF PLL
binary 4-bit swallow counter
(0
≤
IF_A
≤
15)
Preset divide ratio of the IF PLL
binary 9-bit programmable counter
(1
≤
IF_B
≤
511)
Preset divide ratio of the IF PLL
binary 9-bit programmable
reference counter
(2
≤
IF_R
≤
511)
IF_B :
IF_R :
From the above equation and with the SPI_DEF bit set to 1,
LMX2542 generates a fixed IF frequency of 367.20 MHz as
follows:
f
Fin
(MHz)
367.20
IF_B
IF_A
f
OSCin
/ IF_R
(kHz)
120
191
4
L
www.national.com
11
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