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參數(shù)資料
| 型號(hào)： | LMX2532 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinum Frequency Synthesizer System with Integrated VCOs |
| 中文描述： | PLLatinum頻率合成系統(tǒng)的集成和VCO |
| 文件頁數(shù)： | 8/18頁 |
| 文件大?。?/td> | 189K |
| 代理商： | LMX2532 |
Functional Description
(Continued)
TABLE 4. IF Frequencies
Device Type
f
VCO
(MHz)
440.76
170.67
367.20
IF_B
IF_A
f
OSC
/IF_R
(kHz)
120
120
120
LMX2522LQ1635
LMX2532LQ0967
LMX2532LQ1065
229
88
191
9
15
4
VCO FREQUENCY TUNING
The center frequency of the RF VCO is mainly determined
by the resonant frequency of the tank circuit. This tank circuit
is implemented on-chip and requires no external inductor.
The LMX2522/32 actively tunes the tank circuit to the re-
quired frequency with the built-in tracking algorithm.
BANDWIDTH CONTROL AND FREQUENCY LOCK
During the frequency acquisition period, the loop bandwidth
is significantly extended to achieve frequency lock. Once
frequency lock occurs, the PLL will return to a steady state
condition with the loop bandwidth set to its nominal value.
The transition between acquisition and lock modes occurs
seamlessly and extremely fast, thereby, meeting the strin-
gent requirements associated with lock time and phase
noise. Several controls (BW_DUR, BW_CRL and BW_EN)
are used to optimize the lock time performance.
SPURIOUS REDUCTION
To improve the spurious performance of the device one of
two types of spurious reduction schemes can be selected:
A continuous optimization scheme, which tracks the en-
vironmental and voltage variations, giving the best spuri-
ous performance over changing conditions
A one time optimization scheme, which sets the internal
compensation values only when the PLL goes into a
locked state.
The spurious reduction can also be disabled, but it is recom-
mended that the continuous optimization mode be used for
normal operation.
POWER DOWN MODE
The LMX2522 and LMX2532 include a power down mode to
reduce the power consumption. The LMX2522/32 enters into
the power down mode either by taking the CE pin LOW or by
setting the power down bits in Register R1.
Table 5
summa-
rizes the power down function. If CE is set LOW, the circuit is
powered down regardless of the register values. When CE is
HIGH, the IF and RF circuitry are individually powered down
by setting the register bits.
TABLE 5. Power Down Configuration
CE Pin
0
1
1
1
1
RF_EN
X
0
0
1
1
IF_EN
X
0
1
0
1
RF Circuitry
OFF
OFF
OFF
ON
ON
IF Circuitry
OFF
OFF
ON
OFF
ON
X = Don’t care.
LOCK DETECT
The LD output can be used to indicate the lock status of the
RF PLL. Bit 21 in Register R0 determines the signal that
appears on the LD pin. When the RF PLL is not locked, the
LD pin remains LOW. After obtaining phase lock, the LD pin
will have a logical HIGH level. The output can also be
programmed to be ground at all times.
TABLE 6. Lock Detect Modes
LD Bit
0
1
Mode
Disable (GND)
Enable
TABLE 7. Lock Detect Logic Table
RF PLL Section
Locked
Not Locked
LD Output
HIGH
LOW
Note 9:
LD output becomes low when the phase error is larger than t
W2
.
Note 10:
LD output becomes high when the phase error is less than t
W1
for
four or more consecutive cycles.
Note 11:
Phase Error is measured on leading edge. Only errors greater than
t
W1
and t
W2
are labeled.
Note 12:
t
W1
and t
W2
are equal to 10 ns.
Note 13:
The lock detect comparison occurs with every 64
th
cycle of f
R
and
f
N
.
20067205
FIGURE 1. Lock Detect Timing Diagram Waveform
L
www.national.com
8
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