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參數(shù)資料
| 型號： | LMX2532 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinum Frequency Synthesizer System with Integrated VCOs |
| 中文描述： | PLLatinum頻率合成系統(tǒng)的集成和VCO |
| 文件頁數(shù)： | 10/18頁 |
| 文件大小： | 189K |
| 代理商： | LMX2532 |
Programming Description
CONTROL REGISTER CONTENT MAP
The serial interface has a 24-bit shift register to store the incoming data bits temporarily. The incoming Data is loaded into the shift
register from MSB to LSB. The Data is shifted at the rising edge of the Clock signal. When the Latch Enable signal transitions from
LOW to HIGH, the data stored in the shift register is transferred to the proper register depending on the address bit settings. The
selection of the particular register is determined by the control bits indicated in boldface text.
At initial start-up, the MICROWIRE loading requires 4 default words (registers R3, loaded first, to R0, loaded last).After the device
has been initially programmed, the RF VCO frequency can be changed using a single register (R0). If an IF frequency other than
the default value for the device is desired the SPI_DEF bit should be set to 0, the desired values for IF_A, IF_B, and IF_R entered
and words R6 to R0 should be sent.
The control register content map describes how the bits within each control register are allocated to the specific control functions.
Complete Register Map
R
MSB
SHIFT REGISTER BIT LOCATION
LSB
23
22
21
20
19
18 17 16 15 14 13 12
11
10 9 8 7 6 5
4
3
2
1 0
R0
(Default)
SPI_
DEF
RF_
SEL
RF_
LD
SP
UR_
CRL
1
RF_B
[3:0]
RF_A
[2:0]
RF_FN
[10:0]
0 0
R1
(Default)
IF_
FREQ
[1:0]
IF_
CUR[1:0]
BW_
DUR
[1:0]
0
OSC_
FREQ
0
0
0
0
0
0
0
SPUR_
RDT
[1:0]
1
0
0 1 0 1 OB_
CRL
[1:0]
RF_
EN
IF_
EN
0 1
R2
(Default)
R3
(Default)
0
0
1
0
0
1
1
1
0
1
0
1 0 1 0 0
0
1
0
1 0
BW_
CRL
[1:0]
0
BW_
EN
1
0
1
1
1
1
0
1
0
0 0 1 1 0
VCO_
CUR
[1:0]
0
1 1
R4
0
1
0
0
0
IF_A
[3:0]
1
IF_B
[8:0]
0
1
1 1
R5
0
0
1
1
0
0
0
0
0
IF_R
[8:0]
0
0
1
1
1 1
R6
1
0
0
0
0
0
0
0
0
0
0
0
0
0 0 0 0
0
1
1
1
1 1
NOTE:
Bold
numbers represent the address bits.
L
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