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參數(shù)資料
| 型號： | LMX2532 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinum Frequency Synthesizer System with Integrated VCOs |
| 中文描述： | PLLatinum頻率合成系統(tǒng)的集成和VCO |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 189K |
| 代理商： | LMX2532 |
Programming Description
(Continued)
R3 REGISTER
The R3 register address bits (R3 [2:0]) are “011”.
Register R3 contains the controls for the phase lock bandwidth controls (BW_DUR, BW_CRL and BW_EN). The duration of the
digital controller portion of the bandwidth control is set by BW_DUR [1:0]. The minimum time set with 00 and increasing durations
to the maximum value set with 11. BW_CRL [1:0] sets the phase offset criterion for the bandwidth controller. Once the phase
offset between the reference clock and the divided VCO signal are within the set criterion, the bandwidth control stops. The
maximum phase offset is set with 00 and decreases to the minimum value set with 11. BW_EN enables the bandwidth control in
the locking state.
The VCO dynamic current is also controlled in register R3 with VCO_CUR [1:0]. The minimum value corresponds to 00 and
increases to a maximum value set at 11.
R3 REGISTER
R
MSB
23
SHIFT REGISTER BIT LOCATION
16
15
14
13
Data Field
LSB
0
22
21
20
19
18
17
12
11
10
9
8
7
6
5
4
3
2
1
Address
Field
1
R3
(Default)
BW_
DUR
[1:0]
BW_
CRL
[1:0]
BW_
EN
1
0
1
1
1
1
0
1
0
0
0
1
1
0
VCO_
CUR
[1:0]
0
1
Name
BW_DUR [1:0]
Functions
Bandwidth Duration
00 = Minimum value (Recommended)
01 =
10 =
11 = Maximum value
Bandwidth Control
00 = Maximum phase offset (Recommended)
01 =
10 =
11 = Minimum phase offset
Bandwidth Enable
0 = Disable
1 = Enable (Recommended)
VCO Dynamic Current
00 = Minimum value
01 =
10 =
11 = Maximum value (Recommended)
BW_CRL [1:0]
BW_EN
VCO_CUR [1:0]
L
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