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參數(shù)資料
| 型號(hào)： | LMX2353TMX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum⑩ Fractional N Single 2.5 GHz Frequency Synthesizer |
| 中文描述： | PHASE LOCKED LOOP, 2500 MHz, PDSO16 |
| 封裝： | PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大小： | 210K |
| 代理商： | LMX2353TMX |
2.0 Programming Description
(Continued)
2.2 R REGISTER
If the ADDRESS[1:0] field is set to 1 0 data is transferred from the 24-bit shift register into the R register which sets the PLL’ s
15-bit R-counter divide ratio when Latch Enable (LE) signal goes high. The divide ratio is put into the R_CNTR[14:0] field and is
described in section 2.2.1. The divider ratio must be
≥
3. The bits used to control the voltage doubler (V2_EN), Delay Lock Loop,
(DLL_MODE), Charge Pump (CP_WORD) are detailed in section 2.2.2 -2.2.4 below.
Most Significant Bit
23
22
SHIFT REGISTER BIT LOCATION
14
13
12
11 10
Data Field
Least Significant Bit
3
2
1
Address Field
21
20
19
18
17
16
15
9
8
7
6
5
4
0
DLL_
MODE
R
_21
V2_
EN
R
_20
CP_WORD[4:0]
R_CNTR[14:0]
1
0
R
_19
R
_18
R
_17
R
_16
R
_15
R
_14
R
_13
R
_12
R
_11
R
_10
R
_9
R
_8
R
_7
R
_6
R
_5
R
_4
R
_3
R
_2
R
_1
R
_0
2.2.1 Reference Divide Ratio
If the ADDRESS[1:0] field is set to 1 0 data is transferred MSB first from the 24-bit shift register into a latch which sets the 15-bit
R Counter, R_CNTR[14:0]. Serial data format is shown below.
(R_CNTR)
R_CNTR[14:0]
R_8
R_7
0
0
1
Divide Ratio
3
4
32,767
R_14 R_13 R_12 R_11 R_10
0
0
0
0
0
0
1
1
1
R_9
0
0
1
R_6
0
0
1
R_5
0
0
1
R_4
0
0
1
R_3
0
0
1
R_2
0
1
1
R_1
1
0
1
R_0
1
0
1
0
0
1
0
0
1
0
0
1
Note:
R-counter divide ratio must be from 3 to 32,767.
2.2.2 V2_EN
The V2_EN bit when set high enables the voltage doubler for the charge pump supply.
(R_20)
Bit
Location
R_20
Function
0
1
V2_EN
Voltage Doubler Enable
Disable
Enabled
2.2.3 DLL_MODE
The DLL_MODE bit should be set to 1 for normal usage.
(R_21)
Bit
Location
Function
Delay Line Loop
Calibration Mode
0
1
DLL_MODE
R_21
Slow
Fast
2.2.4 CP_WORD
(R_15-R_19)
R_19
CP_8X
R_18
CP_4X
R_17
CP_2X
R_16
CP_1X
R_15
PD_POL
2.2.4.1 Charge Pump Output Truth Table
ICP
O
μA (typ)
R_19
CP_8X
0
0
0
0
-
1
-
1
R_18
CP_4X
0
0
0
0
-
0
-
1
R_17
CP_2X
0
0
1
1
-
0
-
1
R_16
CP_1X
0
1
0
1
-
0
-
1
100
200
300
400
-
900
-
1600
www.national.com
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| LMX2354SLBX/NOPB | 功能描述:IC FREQ SYNTH DUAL 24-LAMCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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