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參數(shù)資料
| 型號： | LMX2353TMX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum⑩ Fractional N Single 2.5 GHz Frequency Synthesizer |
| 中文描述： | PHASE LOCKED LOOP, 2500 MHz, PDSO16 |
| 封裝： | PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 210K |
| 代理商： | LMX2353TMX |
2.0 Programming Description
(Continued)
2.4.2.4 Typical Lock Detecting Timing
2.5 F2 REGISTER
If theADDRESS[1:0] field is set to 0 1, data is transferred from the 24-bit shift register into the F2 register when Latch Enable (LE)
signal goes high. The F2 register sets the CMOS output word bit CMOS[3:0] and the power down mode bit PWDN_MODE. The
rest of the bits F2_0 - F2_14, and F2_20-F_21 are Don’t Care.
Most Significant Bit
23
22
SHIFT REGISTER BIT LOCATION
14
13
12
11
Data Field
Least Significant Bit
3
2
1
Address Field
21
20
19
18
17
16
15
10
9
8
7
6
5
4
0
0
0
PWDN_
MODE
F2
_19
CMOS[3:0]
These bits should be set to zero
0
0
F2
_21
F2
_20
F2
_18
F2
_17
F2
_16
F2
_15
F2
_14
F2
_13
F2
_12
F2
_11
F2
_10
F2
_9
F2
_8
F2
_7
F2
_6
F2
_5
F2
_4
F2
_3
F2
_2
F2
_1
F2
_0
Note:
0 denotes setting the bit to zero
2.5.1 PWDN_MODE
See section 2.3.2 describing the control word and power down.
(F2_19)
2.5.2 Programmable CMOS Outputs
(F2_15–F2_18)
F2_18
FastLock
F2_17
TEST
F2_16
OUT_1
F2_15
OUT_0
2.5.3 OUT0/OUT1 Truth Table
Bit
Location
Function
0
1
OUT_0
F2_15
Set the output logic level of
OUT0 pin
Set the output logic level of
OUT1 pin
Test
FastLock Mode
LOW
HIGH
OUT_1
F2_16
LOW
HIGH
TEST
FastLock
The CMOS[3:0] 4-bit register selects one of three modes for the OUT_0 and OUT_1 pins. The OUT_0 and OUT_1 pins are nor-
mally used as general purpose CMOS outputs or as part of a fastlock scheme. There is also a production test mode that overrides
the other two normal modes when activated.
GENERAL PURPOSE CMOS OUTPUT MODE: The general purpose CMOS output mode is selected when the Fastlock bit
(F2_F18) and TEST bit (F2_17) are set LOW. The logic levels of the OUT_0 bit (F2_15) and OUT_1 bit (F2_16) then determine
the logic states of the OUT_0 and OUT_1 pins.
FASTLOCK MODE: The Fastlock bit (F2_18) selects between the general purpose CMOS output or fastlock modes. The fastlock
mode is selected when the fastlock bit is HIGH. The fastlock mode allows the user to open up the loop bandwidth momentarily
while acquiring lock by increasing the charge pump output current magnitude while simultaneously switching in a second resistor
element to ground via the OUT0 output pin.
F2_17
F2_18
Normal Operation
CMOS Output Mode
Test Mode
FastLock Mode
DS101124-7
www.national.com
13
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相關代理商/技術參數(shù) |
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|---|---|
| LMX2353TMX/NOPB | 功能描述:IC FREQ SYNTH 2.5GHZ 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| LMX2354 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer |
| LMX2354SLB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer |
| LMX2354SLBX | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| LMX2354SLBX/NOPB | 功能描述:IC FREQ SYNTH DUAL 24-LAMCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
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