參數(shù)資料
型號(hào): LMX2315MDA
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類(lèi): PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 1200 MHz, UUC
封裝: DIE
文件頁(yè)數(shù): 13/25頁(yè)
文件大小: 452K
代理商: LMX2315MDA
Application Information (Continued)
MEASUREMENT RESULTS
(Example
2)
TLW12339 – 34
FIGURE 10 PLL Reference Spurs
The reference spurious level is k b65 dBc due to the loop
filter attenuation and the low spurious noise level of the
LMX2320
TLW12339 – 36
FIGURE 12 PLL Phase Noise 20 kHz Offset
The phase noise level at 20 kHz offset is b80 dBcHz
TLW12339 – 35
FIGURE 11 PLL Phase Noise
150 Hz Offset
The phase noise level at 150 Hz offset is b811 dBcHz
The spurs at 60 and 180 Hz offset are due to 60 Hz line
noise from the power supply
TLW12339 – 37
FIGURE 13 Frequency Jump Lock Time
Of concern in any PLL loop filter design is the time it takes
to lock in to a new frequency when switching channels
Fig-
ure 13 shows the switching waveforms for a frequency jump
of 16509 MHz to 16839 MHz By narrowing the frequency
span of the HP53310A Modulation Domain Analyzer en-
ables evaluation of the frequency lock time to within
g
1 kHz The lock time is seen to be less than 500 ms for a
frequency jump of 33 MHz
http
www nationalcom
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