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參數(shù)資料
| 型號(hào)： | LMX1600SLB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum⑩ Low Cost Dual Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, QCC16 |
| 封裝： | CSP-16 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 196K |
| 代理商： | LMX1600SLB |
2.0
Programming Description
(Continued)
2.3.4
If the Control Bits (CTL[1:0]) are 1 1 when LE transitions high, data is transferred from the 18-bit shift register into the MAIN_N
register latch which sets 16-bit programmable N divider value. The Main N divider is a 16-bit counter which is fully programmable
from 992 to 65,535 for 2 GHz option and from 240 to 65,535 for 1.1 GHz option. The MAIN_N register consists of the 5-bit (2 GHz
option) or 4-bit (1.1 GHz option) swallow counter (MAIN_A_CNTR) and the 11-bit (2 GHz option) or 12-bit (1.1 GHz option) pro-
grammable counter (MAIN_B_CNTR). Serial data format for the MAIN_N register latch shown below. The divide ratio must be
≥
992 (2 GHz option) or 240 (1.1 GHz option) for a continuous divide range. The divide ratio is programmed using the bits
MAIN _A_CNTR and MAIN_B_CNTR as shown in tables 2.3.5 and 2.3.6 The pulse swallow function which determines the divide
ratio is described in Section 2.3.7.
MAIN_N Register
2 GHz option
First Bit
17
SHIFT REGISTER BIT LOCATION
11
10
9
AUX_B_CNTR[10:0]
Last Bit
1
1
16
15
14
13
12
8
7
6
5
4
3
2
0
1
MAIN_N
AUX_A_CNTR[4:0]
1.1 GHz option
First Bit
17
SHIFT REGISTER BIT LOCATION
11
10
9
AUX_B_CNTR[11:0]
Last Bit
1
1
16
15
14
13
12
8
7
6
5
AUX_A_CNTR[3:0]
4
3
2
0
1
MAIN_N
2.3.5
Swallow Counter Divide Ratio (Main A COUNTER)
2 GHz option (5 bit)
Swallow
Count
(A)
0
1
31
MAIN_A_CNTR
4
0
0
1
3
0
0
1
2
0
0
1
1
0
0
1
0
0
1
1
Note 11:
Swallow Counter Value: 0 to 31
1.1 GHz option (4 bit)
Swallow
Count
(A)
0
1
15
MAIN_A_CNTR
3
0
0
1
2
0
0
1
1
0
0
1
0
0
1
1
Note 12:
Swallow Counter Value: 0 to 15
2.3.6
Programmable Counter Divide Ratio (Main B COUNTER)
2 GHz option (11 bit)
MAIN_B_CNTR
7
0
0
1
Divide Ratio
3
4
2,047
10
0
0
1
9
0
0
1
8
0
0
1
6
0
0
1
5
0
0
1
4
0
0
1
3
0
0
1
2
0
1
1
1
1
0
1
0
1
0
1
Note 13:
Divide ratio: 3 to 2,047 (Divide ratios less than 3 are prohibited)
MAIN_B_CNTR
≥
MAIN_A_CNTR.
See section 2.3.7 for calculation of VCO output frequency.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX1600SLBX | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| LMX1600SLBX/NOPB | 功能描述:IC FREQ SYNTH DUAL 16LAMINATECSP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX1600TM | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Low Cost Dual Frequency Synthesizer |
| LMX1600TM/NOPB | 功能描述:IC FREQ SYNTHESIZER DUAL 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX1600TMX | 功能描述:IC FREQ SYNTHESZR 2.0GHZ 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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