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參數(shù)資料
| 型號： | LMX1600SLB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum⑩ Low Cost Dual Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, QCC16 |
| 封裝： | CSP-16 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 196K |
| 代理商： | LMX1600SLB |
2.0
Programming Description
(Continued)
2.2.2
If the Control Bits (CTL [1:0]) are 1 0 when LE transitions high, data is transferred from the 18-bit shift register into a latch which
sets the Main PLL 12-bit R counter divide ratio and various control functions. The divide ratio is programmed using the bits
MAIN_R_CNTR
as shown in table 2.2.3. The divider ratio must be
≥
2. The charge pump control word (CP_WORD[3:0] ) sets the
charge pump gain and the phase detector polarity as detailed in 2.4.
MAIN_R REGISTER
First Bit
17
CP_WORD[3:0]
SHIFT REGISTER BIT LOCATION
11
10
9
MAIN_R_CNTR[11:0]
Last Bit
1
1
16
15
14
13
12
8
7
6
5
4
3
2
0
0
MAIN_R
2.2.3
(MAIN/AUX R Counter)
12-Bit Programmable Main and Auxiliary Reference Divider Ratio
MAIN_R_CNTR/AUX_R_CNTR
9
8
7
0
0
0
0
0
0
1
1
1
Divide Ratio
2
3
4,095
11
0
0
1
10
0
0
1
6
0
0
1
5
0
0
1
4
0
0
1
3
0
0
1
2
0
0
1
1
1
1
1
0
0
1
1
Note 7:
Legal divide ratio: 2 to 4,095.
2.3
PROGRAMMABLE FEEDBACK (N) DIVIDERS
2.3.1
If the Control Bits ( CTL[1:0]) are 0 1 when LE transitions high, data is transferred from the 18-bit shift register into the AUX_N
register latch which sets the Aux PLL 16-bit programmable N counter value. The AUX_N counter is a 16-bit counter which is fully
programmable from 240 to 65,535 for 1.1 GHz option or from 56 to 32,767 for 500 MHz option. The AUX_N register consists of
the 4-bit swallow counter (AUX_A_CNTR), the 12-bit programmable counter (AUX_B_CNTR). Serial data format is shown below.
The divide ratio (AUX_N_CNTR [13:0]) must be
≥
240 (1.1 GHz option) or
≥
56 (500 MHz option) for a continuous divide range.
The Aux PLL N divide ratio is programmed using the bits AUX_A_CNTR, AUX_B_CNTR as shown in tables 2.3.2.
AUX_N Register
First Bit
17
SHIFT REGISTER BIT LOCATION
11
10
9
AUX_B_CNTR[11:0]
Last Bit
1
0
16
15
14
13
12
8
7
6
5
AUX_A_CNTR[3:0]
4
3
2
0
1
AUX_N
2.3.2
4-BIT Swallow Counter Divide Ratio (Aux A COUNTER)
1.1 GHz option
Swallow
Count
(A)
0
1
15
AUX_A_CNTR
3
0
0
1
2
0
0
1
1
0
0
1
0
0
1
1
Note 8:
Swallow Counter Value: 0 to 15
500 MHz option
Swallow
Count
(A)
0
1
7
AUX_A_CNTR
3
X
X
X
2
0
0
1
1
0
0
1
0
0
1
1
Note 9:
Swallow Counter Value: 0 to 7
X = Don’t Care condition
2.3.3
12-BIT Programmable Counter Divide Ratio (Aux B COUNTER)
AUX_B_CNTR
8
7
0
0
0
0
1
1
Divide Ratio
3
4
4,095
11
0
0
1
10
0
0
1
9
0
0
1
6
0
0
1
5
0
0
1
4
0
0
1
3
0
0
1
2
0
1
1
1
1
0
1
0
1
0
1
Note 10:
Divide ratio: 3 to 4,095 (Divide ratios less than 3 are prohibited)
AUX_B_CNTR
≥
AUX_A_CNTR.
See section 2.3.7 for calculation of VCO output frequency.
7
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相關代理商/技術參數(shù) |
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| LMX1600SLBX | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| LMX1600SLBX/NOPB | 功能描述:IC FREQ SYNTH DUAL 16LAMINATECSP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| LMX1600TM | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Low Cost Dual Frequency Synthesizer |
| LMX1600TM/NOPB | 功能描述:IC FREQ SYNTHESIZER DUAL 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| LMX1600TMX | 功能描述:IC FREQ SYNTHESZR 2.0GHZ 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
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