參數(shù)資料
型號: LM9823
文件頁數(shù): 7/20頁
文件大?。?/td> 245K
代理商: LM9823
AC Electrical Characteristics
(Continued)
Note 13:
PGA Gain Error is the maximum difference between the measured gain for any PGA code and the ideal gain calculated by using the formula
.
Note 14:
Full Channel INL and DNL are tested with CDS disabled, negative signal polarity, and a single OS input with a gain register setting of 1 (000001b) and
an offset register setting of 0 (000000b).
Note 15:
The digital supply current (I
D
) does not include the load, data and switching frequency dependent current required to drive the digital output bus on pins
(D5-D0). The current required to switch the digital data bus can be calculated from: I
SW
= 2 x N
d
x P
sw
x C
L
x V
D
/t
SampCLK
where N
d
is total number of data pins,
P
sw
is the probability of each data bit switching, C
L
is the capacitive loading on each data pin, V
D
is the digital supply voltage and t
SampCLK
is the period of the
SampCLK signal. Since N
d
is 6, P
sw
should be .5 and V
D
is nominally 5V, the switching current can usually be calculated from: I
SW
= 30 x C
L
/t
SampCLK
. For example,
if the capacitive load on each digital output pin (D5-D0) is 20 pF and the period of t
SampCLK
is 1/6 MHz or 167 ns, then the digital switching current would be 7.2
mA. The calculated digital switching current will be drawn through the V
D
pin and should be considered as part of the total power budget for the LM9810/20.
DS100943-72
L
www.national.com
7
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