參數(shù)資料
型號(hào): LM9822CCWM
英文描述: Signal Conditioner
中文描述: 信號(hào)調(diào)理
文件頁(yè)數(shù): 19/20頁(yè)
文件大?。?/td> 245K
代理商: LM9822CCWM
Applications Information
(Continued)
such asADC sampling, and output data bus switching can
potentially affect coincident events such as input signal
sampling or offset DAC settling. One event can interfere
with another by coupling noise on shared resources such
as the supply lines, internal voltage references, or the
silicon substrate.
To optimize the performance of the LM9810/20, Samp-
CLK should be timed so that the input signal hold times do
not coincide with output data switching and ADC clock
transitions. In other words, the rising and falling edges of
SampCLK should not be placed close toADC clock edges
or to output data transitions. SampCLK edges should be
at least 20 ns away from ADC clock edges to avoid
interference between the ADC and the sampler. Samp-
CLK edges should also be placed at least 40 ns after
output data transition times to avoid transition noise cou-
pling.
Figure 11is an example of SampCLK timing that will meet
these requirements at the maximum MCLK frequency of
24 MHz. In Figure 11 SampCLK transitions occur on
MCLK falling edges which will keep them more than 20 ns
away from ADC transitions, and 40 ns after output data
transitions.
L
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