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參數資料
| 型號： | LM9822CCWM |
| 英文描述： | Signal Conditioner |
| 中文描述： | 信號調理 |
| 文件頁數： | 16/20頁 |
| 文件大小： | 245K |
| 代理商： | LM9822CCWM |
Applications Information
(Continued)
NewLine. For example, the R offset and gain settings will
be used for the first conversion following a falling edge on
NewLine if the color mode is set to Single Input Color
(001).
For the Single Input Color, Bayer and Green Stripe
modes, the mux will always connect the OS
input to the
sampler. The offset and gain settings will alternate values
every pixel according to the order indicated by the Sam-
pler and Color Mode register (see Table 2). The first falling
edge of NewLine following a write to the Sampler and
Color Mode register will ready the offset and gain to cycle
through the colors of the first line of the programmed color
mode. Each subsequent falling edge of NewLine will
switch the offset and gain settings to the first color of the
next line. The LM9810/20’s unused OS inputs should not
be left unconnected. All three OS inputs should be tied
together on the LM9810/20 side of the clamp capacitor
(see Figure 8).
For the Line Rate Color mode, the mux will cycle through
the OS
, OS
and OS
inputs after each falling edge of
NewLine. The R, G and B offset and gain settings will be
used when the mux is set to OS
, OS
and OS
input,
respectively. OS
and the R offset and gain settings will
always be used on the first line following a write register 0.
1.5 Data Latency
The latency through the LM9810/20 is a 8 SampCLK
periods plus one MCLK period. The data output on D5 -
D0 (MSBs b11 - b6 or b9 - b4) represents data whose
reference signal was sampled 8 t
SampCLK
+ t
MCLK
+
t
SampSU
earlier (See Figure 1).
1.6 Programmable Gain
The output of the Sampler drives the input of the x3 Boost
gain stage. The gain of the x3 Boost gain is 3 V/V if bit B5
of the current color’s gain register (registers 4, 5 and 6) is
set, or 1 V/V if bit B5 is cleared. The output of the x3 gain
stage is the input to the offset DAC and the output of the
offset DAC is the input to the PGA (Programmable Gain
Amplifier). The PGAprovides 5 bits of gain correction over
a 0.93 V/V to 3 V/V (0.6 to 9.5 dB) range. The x3 Boost
gain stage and the PGA can be combined for an overall
gain range of 0.93 V/V to 9.0 V/V (0.6 to 19 dB). The gain
setting for each color (registers 4, 5 and 6) should be set
during calibration to bring the maximum amplitude of the
strongest pixel to a level just below the desired maximum
output from the ADC. The PGA gain is determined by the
following equation:
(1)
If the x3 Boost gain is enable then the overall signal gain
will be three times the PGA gain.
1.7 Offset DAC
The Offset DAC removes the DC offsets generated by the
sensor and the LM9810/20’s analog signal chain (see
section 1.7.1, Internal Offsets). The DAC value for each
color (registers 1, 2 and 3) should be set during calibration
to the lowest value that still results in an ADC output code
greater than zero for all the pixels when scanning a black
line. With a PGAgain of 1 V/V, each LSB of the offset DAC
typically adds the equivalent of 5 LM9810 LSBs or 20
LM9820 LSBs, providing a total offset adjustment range of
±
150 LM9810 LSBs or
±
590 LM9820 LSBs. The Offset
DAC’s output voltage is given by:
V
DAC
= 9.75 mV x (value in B4 - B0)
In terms of output codes, the offset is given by:
Offset = 5 LSBs x (value in B4 - B0) x PGA Gain (3)
Offset = 20 LSBs x (value in B4 - B0) x PGA Gain (4)
The offset is positive if bit B5 is cleared and negative if B5
is set. Since the analog offset is added before the PGA
gain, the value of the PGA gain must be considered when
selecting the offset DAC values.
(2)
1.7.1 Internal Offsets
Figure 9 is a model of the LM9810/20’s internal offsets.
Equation (5) shows how to calculate the expected output
code given the input voltage (V
IN
), the LM9810/20 internal
offsets (V
OS1
, V
OS2
, V
OS3
), the programmed offset DAC
voltage (V
DAC
), the programmed gains (G
B
, G
PGA
) and
the analog channel gain constant C.
C is a constant that combines the gain error through the
AFE, reference voltage variance, and analog voltage to
digital code conversion into one constant. Ideally, C =
2048 codes/V (4096 codes/2V) for the LM9820 and 512
codes/V (1024 codes/2V) for the LM9810. Manufacturing
tolerances
widen
the
range
Specifications).
of
C
(see
Electrical
D
OUT
= (((V
IN
+ (V
OS1
)G
B
+ V
DAC
+ V
OS2
) G
PGA
+
V
OS1
)C
Equation (6) is a simplification of the output code calcula-
tion, neglecting the LM9810/20’s internal offsets.
D
OUT
= (V
IN
G
B
+ (V
DAC
)G
PGA
C
(5)
(6)
1.8 Power Down Mode
Setting the Power Down (bit B0 of register 7) puts the
device in a low power standby mode. The analog sections
are turned off to conserve power. The digital logic will
continue to operate if MCLK continues, so for minimum
power dissipation MCLK should be stopped when the
DS100943-80
FIGURE 8. OS Connections for Signal Output Sensors
DS100943-81
FIGURE 9. Internal Offset Mode
L
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