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參數(shù)資料
| 型號(hào)： | LM9820 |
| 文件頁(yè)數(shù)： | 8/20頁(yè) |
| 文件大小： | 245K |
| 代理商： | LM9820 |
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Pin Descriptions
Analog Power
This is the positive supply pin for the
analog supply. It should be connected
to a voltage source of +5V and
bypassed to the AGND with a 0.1 μF
monolithic capacitor in parallel with a
10 μF tantalum capacitor.
This is the ground return for the analog
supply.
Analog I/O
Analog Inputs. These inputs (for Red,
Green, and Blue) should be tied to the
sensor’s OS (Output Signal) through DC
blocking capacitors.
Internally generated reference voltage
bypass pin. It should be bypassed to
AGND through a .05 μF monolithic
capacitor.
Voltage reference bypass pins. They
should each be bypassed to AGND
through a .05 μF monolithic capacitor.
Input & Timing Control
Master Clock. The ADC conversion rate
will be a maximum of
1
4
of MCLK.
Nominally 24 MHz.
Sample Clock. SampCLK controls the
conversion rate of the ADC (up to
1
4
of
the MCLK rate) and sample timing. The
signal level is sampled while SampCLK
is low and held on the rising edge of
SampCLK. When CDS is enabled, the
falling edge of SampCLK causes the
CCD reference level to be held. If CDS
is not enabled, V
REF
, or V
REF
is held
on the falling edge of SampCLK,
depending on the programmed signal
polarity. SampCLK is also used with
NewLine to clamp the external coupling
capacitors.
V
A
AGND
OS
R
, OS
G
,
OS
B
RefBypass
V
REF
,
V
REFMID
,
V
REF
MCLK
SampCLK
L
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