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| 型號(hào)： | LM9820 |
| 文件頁(yè)數(shù)： | 18/20頁(yè) |
| 文件大?。?/td> | 245K |
| 代理商： | LM9820 |
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Applications Information
(Continued)
(13)
For example, if a sensor has 18 black reference pixels
and f
is 2 MHz with a 50% duty cycle, then t
CLAMP
is 4.5 μs.
The following figure takes the number of optical black
pixels, the amount of time (per pixel) that the clamp is
closed, the sensor’s output impedance, and the desired
accuracy of the final clamp voltage and provides the
maximum clamp capacitor value that allows the clamp
capacitor to settle to the desired accuracy within a single
line:
(14)
Where t
is the amount of time (per line) that the
clamp is on, R
is the output impedance of the CCD
plus 50
for the LM9810/20’s internal clamp switch, and
accuracy is the ratio of the worst-case initial capacitor
voltage to the desired final capacitor voltage. If t
is
4.5 μs, the output impedance of the sensor is 1500
, the
worst case voltage change required across the capacitor
(before the first line) is 5V, and the desired accuracy after
clamping is to within 0.1V (accuracy = 5/0.1 = 50), then:
(15)
The final value for C
CLAMP
should be less than or equal to
C
CLAMP MAX
, but no less than C
CLAMP MIN
.
In some cases, depending primarily on the choice of
sensor, C
CLAMP MAX
may actually be less than C
CLAMP
MIN
, meaning that the capacitor can not be charged to its
final voltage during the black pixels at the beginning of a
line and hold its voltage without drooping for the duration
of that line. This is usually not a problem because in most
applications the sensor is clocked continuously as soon
as power is applied. In this case, a larger capacitor can be
used (guaranteeing that the C
requirement is
met), and the final clamp voltage is forced across the
capacitor over multiple lines. This equation calculates how
many lines are required before the capacitor settles to the
desired accuracy:
(16)
Using the values shown before and a clamp capacitor
value of 0.01 μF, this works out to be:
(17)
In this example, a 0.01 μF capacitor takes 14 lines after
power-up to charge to its final value. On subsequent lines,
the only error will be the droop across a single line which
should be significantly less than the initial error.
If the
LM9810/20 is operating in CDS mode and multiple
lines are used to charge up the clamping capacitors
after power-up, then a clamp capacitor value of 0.01
μF should be significantly greater than the calculated
C
CLAMP MIN
value and can virtually always be used
.
If the LM9810/20 is operating in CIS mode, then signifi-
cantly larger clamp capacitors must be used. Fortunately,
the output impedance of most CIS sensors is significantly
smaller than the output impedance of CCD sensors, and
R
will be dominated by the 50
from the LM9810/
20’s internal clamp switch. With a smaller R
CLAMP
value,
the clamp capacitors will charge faster.
3.0 PERFORMANCE CONSIDERATIONS
3.1 Power Supply
The LM9810/20 should be powered by a single +5V
source. The analog supplies (V
) and the digital supply
(V
) are brought out individually to allow separate bypass-
ing for each supply input. They should not be powered by
two or more different supplies.
In systems with separate analog and digital +5V supplies,
all the supply pins of the LM9810/20 should be powered
by the analog +5V supply. Each supply input should be
bypassed to its respective ground with a 0.1 μF capacitor
located as close as possible to the supply input pin. A
single 10 μF tantalum capacitor should be placed near the
V
A
supply pin to provide low frequency bypassing.
To minimize noise, keep the LM9810/20 and all analog
components as far as possible from noise generators,
such as switching power supplies and high frequency
digital busses. If possible, isolate all the analog compo-
nents and signals (OS, reference inputs and outputs, V
A
,
AGND) on an analog ground plane, separate from the
digital ground plane. The two ground planes should be
tied together at a single point, preferably the point where
the power supply enters the PCB.
3.2 SampCLK Timing
SampCLK is used to time the stages of the LM9810/20’s
sampler, offset DAC and programmable gain amplifier. To
allow for optimum input signal sampling times, SampCLK
may be applied asynchronously to MCLK. The LM9810/
20’s ADC is synchronized with the AFE (including the
sampler, the offset DAC and the PGA) by MCLK.
The LM9810/20’s internal ADC clock is created through a
combination of the applied SampCLK and MCLK signals.
MCLK is used to synchronize the applied SampCLK sig-
nal. The internal ADC clock will go low after the falling
edge of SampCLK is clocked by a rising of MCLK. The
ADC clock will stay low for two MCLK cycles and then go
high. It will stay high until the next falling edge of Samp-
CLK is clocked by MCLK. Figure 11 illustrates this Samp-
CLK, MCLK, and ADC clock timing relationship.
The LM9810/20 is a densely designed, mixed-signal,
monolithic semiconductor. In creating the timing for the
LM9810/20, it must be considered that internal events,
DS100943-83
FIGURE 11. LM9810/20 Relative Event Timing
L
www.national.com
18
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