參數(shù)資料
型號: LM9811CCV
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 模擬信號調(diào)理
英文描述: 10-Bit Greyscale/30-Bit Color Linear CCD Sensor Processor
中文描述: SPECIALTY ANALOG CIRCUIT, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 8/36頁
文件大小: 605K
代理商: LM9811CCV
Pin Descriptions
CCD Driver Signals
Digital Output. CCD clock signal, phase
1.
Digital Output. CCD clock signal, phase
2.
Digital Output. Reset pulse for the CCD.
Digital Output. Transfer pulse for the
CCD.
Analog I/O
Analog Input. This is the OS (Output
Signal) from the CCD. The maximum
peak signal that can be accurately
digitized is equal to the voltage at REF
IN, typically 1.225V.
Analog Inputs. These two pins are the
system reference voltage inputs and
should be tied together to a 1.225V
voltage source and bypassed to AGND
with a 0.1 μF monolithic capacitor.
Analog Output. This reference voltage is
developed internally by the LM9811,
and is equal to 3 times REF IN. It
should be bypassed to AGND with a
0.1 μF monolithic capacitor.
Analog Output. This reference voltage is
developed internally by the LM9811,
and is equal to 2 times REF IN. It
should be bypassed to AGND using a
0.1 μF monolithic capacitor.
Analog Inputs/Outputs. These pins are
used for testing the device during
manufacture and should be left
unconnected.
Configuration Register I/O
Digital Input. Serial Data Input pin.
Digital Output. Serial Data Output pin.
Digital Input. This is the serial data
clock, used to clock data in through SDI
and out through SDO. SCLK is
asynchronous to MCLK. Input data is
latched and output data is changed on
the rising edge of SCLK.
Digital Input. This is the Chip Select
signal for writing to the Configuration
Register through the serial interface.
This input must be low in order to
communicate with the Configuration
Register. This pin is used for serial I/O
only–it has no effect on any other
section of the chip.
Digital Coefficient I/O
Digital Inputs. Correction Coefficient
Databus. This is the 8-bit data path for
the gain adjust PGA, used during line
scan.
φ
1
φ
2
RS
TR
OS
REF IN
REF OUT
HI
REF OUT
MID
V
TEST1
,
V
TEST2
SDI
SDO
SCLK
CS
CD0 (LSB)–
CD7 (MSB)
CCLK
Digital Output. This is the signal that is
used to clock the Gain coefficients into
the LM9811. Data is latched on the
rising edge of CCLK.
Digital Output I/O
Digital Outputs. Pixel Output Databus.
This data bus outputs the 10-bit digital
output data during line scan.
Digital Output. This is the End of
Conversion signal from the ADC
indicating that new pixel data is
available.
Digital Input. Taking this input low
places the data stored in the output
latch on the bus. When this input is high
the DD0–DD9 bus is in TRI-STATE.
General Digital I/O
Digital Input. This is the 12MHz (typical)
master system clock.
Digital Input. A low-to-high transition on
this input begins a line scan operation.
The line scan operation terminates
when this input is taken low.
Analog Power
This is the positive supply pin for the
analog supply. It should be connected
to a voltage source of +5V and
bypassed to AGND with a 0.1 μF
monolithic capacitor in parallel with a
10 μF tantalum capacitor.
This is the ground return for the analog
supply.
Digital Power
This is the positive supply pin for the
digital supply. It should be connected to
a voltage source of +5V and bypassed
to DGND with a 0.1 μF monolithic
capacitor.
This is the ground return for the digital
supply.
This is the positive supply pin for the
digital supply for the LM9811’s I/O. It
should be connected to a voltage
source of +3V to +5V and bypassed to
DGND
(I/O)
with a 0.1 μF monolithic
capacitor. If the supply for this pin is
different than the supply for V
A
and V
D
,
it should also be bypassed with a 10 μF
tantalum capacitor.
This is the ground return for the digital
supply for the LM9811’s I/O.
NC
All pins marked NC (no connect) should
be left floating. Do not tie NC pins to
ground., power supplies, or any other
potential or signal.
DD0 (LSB)–
DD9 (MSB)
EOC
RD
MCLK
SYNC
V
A
AGND
V
D
DGND
V
D(I/O)
DGND
(I/O)
NC
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