參數(shù)資料
型號： LM81CIMTX-3
英文描述： Single-Ended Data Acquisition System
中文描述： 單端數(shù)據(jù)采集系統(tǒng)
文件頁數(shù)： 23/33頁
文件大?。?/td> 414K
代理商： LM81CIMTX-3
Functional Description
(Continued)
individual masks for each Interrupt. As described in Section
3.3, the hardware Interrupt line can also be enabled/disabled
in the Configuration Register.
T_CRIT_A interrupt is dedicated to temperature and is
indicated in Extended Mode Register 1. Extended Mode
Register 1 controls T_CRIT_A.
9.1 Interrupt Clearing
Reading a Status Register will output the contents of the
Register, and reset the Register. A subsequent read done
before the analog “round-robin” monitoring loop is complete
will indicate a cleared Register.Allow at least 820 ms to allow
all Registers to be updated between reads. In summary, the
Interrupt Status Register clears upon being read, and
requires at least 400 ms to be updated. When the Interrupt
Status Register clears, the hardware interrupt line will also
clear until the Registers are updated by the monitoring loop.
The hardware Interrupt line (INT) is cleared with the
INT_Clear bit, which is Bit 3 of the Configuration Register.
When this bit is high, the LM81 monitoring loop will stop. It
will resume when the bit is low.
10.0 RESET I/O
RESET is intended to provide a master reset to devices
connected to this line. INT Mask Register 2, Bit 7, must be
set high to enable this function. Setting Bit 4 in the
Configuration Register high outputs a least 20 ms low on this
line, at the end of which Bit 4 in the Configuration Register
automatically clears. Again, the label for this pin is only its
suggested use. In applications where the RESET capability
is not needed it can be used for any type of digital control
that requires a 20 ms active low open-drain output.
RESET operates as an input when not activated by the
Configuration Register. Setting this line low will reset all of
the registers in the LM81 to their power on default state. All
Value RAM locations will not be affected except for the DAC
Data Register.
11.0 NAND TREE TESTS
A NAND tree is provided in the LM81 for Automated Test
Equipment
(ATE)
board
DACOut/NTEST_IN, T_CRIT_A, V
+
and GND pins are
excluded
from
NAND
tree
NTEST_IN high before the first write to the configuration
register activates the NAND Tree test mode. After the first
write to the configuration register the NAND Tree test mode
cannot be reactivated. To perform a NAND tree test all pins
included in the NAND tree should be driven to 1 forcing the
A0/NTEST_OUT high. Each individual pin starting with A1
and
concluding
with
SMBData
NTEST_IN, T_CRIT_A, V
+
and GND) can be taken low with
the resulting toggle observed on the A0/NTEST_OUT pin.
Allow for a typical propagation delay of 500 ns.
level
connectivity
testing.
testing.
Taking
DACOut/
(excluding
DACOut/
DS100072-29
L
www.national.com
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LM8-1M.5M.1 制造商:Banner Engineering 功能描述:LM8-1M.5M.1 LOGIC MOD MULTIBM
LM81-S 功能描述:基本/快動開關(guān) Foot Switch RoHS:否 制造商:Omron Electronics 觸點形式:SPDT 執(zhí)行器:Lever 電流額定值:5 A 電壓額定值 AC:250 V 電壓額定值 DC:30 V 功率額定值: 工作力:120 g IP 等級:IP 67 NEMA 額定值: 端接類型:Wire 安裝:Panel
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