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參數(shù)資料
| 型號(hào)： | LM78CCVF-J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Microprocessor System Hardware Monitor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP44 |
| 封裝： | 10 X 10 MM, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 7/31頁 |
| 文件大?。?/td> | 424K |
| 代理商： | LM78CCVF-J |
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AC Electrical Characteristics
(Note 13) The following specifications apply for +4.25 V
DC
≤
V
CC
≤
+5.75 V
DC
unless otherwise specified.
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
=
25C.
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
ISA TIMING CHARACTERISTICS
f
SYSCLK
t
CS
(setup)
t
CS
(hold)
t
SA
(setup)
t
SA
(hold)
ISA WRITE TIMING
t
SDWR
(setup)
t
SDWR
(hold)
t
WR
(setup)
System Clock (SYSCLK) Input Frequency
CS Active to IORD/IOWR Active
IORD/IOWR Inactive to CS Inactive
Address Valid to IORD/IOWR Active
IORD/IOWR Inactive to Address Invalid
8.33
MHz
ns (min)
ns (min)
ns (min)
ns (min)
10
10
30
10
Data Valid to IOWR Active
IOWR Inactive to Data Invalid
IOWR Active to Rising Edge of SYSCLK
5
5
20
ns (min)
ns (min)
ns (min)
DS012873-4
The delay between consecutive IORD and IOWR pulses should be greater than 50 ns to ensure that an Power-on reset does not
occur unintentionally. (See
Section 3.2
‘Resets’ )
FIGURE 1. ISA Bus Write Timing Diagram
L
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