參數(shù)資料
型號(hào): LM5026SDX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: Active Clamp Current Mode PWM Controller
中文描述: 3 A SWITCHING CONTROLLER, 660 kHz SWITCHING FREQ-MAX, DSO16
封裝: 5 X 5 MM, EXPOSED PAD, LLP-16
文件頁(yè)數(shù): 17/23頁(yè)
文件大?。?/td> 936K
代理商: LM5026SDX
Applications Information
(Continued)
UNDER-VOLTAGE LOCKOUT (UVLO)
When the UVLO pin voltage is below 0.4V the controller is in
a low current shutdown mode. When the UVLO pin voltage is
greater than 0.4V but less than 1.25V the controller is in
standby mode. When the UVLO pin voltage is greater than
1.25V the controller is fully enabled. Typically, two external
resistors program the minimum operational voltage for the
power converter as shown in
Figure 13
. When UVLO pin
voltage is above the 1.25V threshold, an internal 20 μA
current source is enabled to raise the voltage at the UVLO
pin, thus providing threshold hysteresis. Resistance values
for R1 and R2 can be determined from:
R1 = V
HYS
/ 20 μA
Where V
is the desired turn-on voltage and V
is the
desired UVLO hysteresis at V
. For example, if the
LM5026 is to be enabled when V
reaches 33V, and
disabled when V
is decreased to 30V, R1 calculates to
150 k
, and R2 calculates to 5.9 k
. The voltage at the
UVLO pin should not exceed 6V at any time. Be sure to
check both the power and voltage rating for the selected R1
resistor.
Remote configuration of the controller’s operational modes
can be accomplished with open drain device(s) connected to
the UVLO pin as shown in
Figure 14
.
OSCILLATOR (RT, SYNC)
Oscillator (RT, SYNC) The oscillator frequency is generally
selected in conjunction with the design of the system mag-
netic components along with the volume and efficiency goals
for a given power converter design. The total RT resistance
at the RT pin sets the oscillator frequency. The RT resistors
should be one of the first components placed and connected
when designing the PC board. Direct, short connections to
each side of the RT resistors (RT, DCL and AGND pins) are
recommended .
The SYNC pin can be used to synchronize the internal
oscillator to an external clock. An open drain output is the
recommended interface from the external clock to the SYNC
pin. The clock pulse width should be greater than 15 ns. The
external clock must be a
higher frequency
than the free
running frequency set by the RT resistor. Multiple LM5026
devices can be synchronized together simply by connecting
the devices SYNC pins together. Care should be taken to
ensure the ground potential differences between devices are
minimized. In this configuration all of the devices will be
synchronized to the highest frequency device.
VOLTAGE FEEDBACK (COMP)
The COMP pin is designed to accept the voltage loop feed-
back error signal from the regulated output via an error
amplifier and (typically) an optocoupler. In a typical configu-
ration, VOUT is compared to a precision reference voltage
by the error amplifier. The amplifier’s output drives the opto-
coupler, which in turn drives the COMP pin. The parasitic
capacitance of the optocoupler often limits the achievable
loop bandwidth for a given power converter. The optocoupler
LED and detector junction capacitance produce a low fre-
quency pole in the voltage regulation loop. The LM5026
current controlled optocoupler interface (COMP) previously
described, greatly increases the pole frequency associated
with the optocoupler.
CURRENT SENSE (CS)
The CS pin receives an input signal representative of the
transformer primary current, either from a current sense
transformer (
Figure 15
) or from a resistor in series with the
source of the primary switch (
Figure 16
). In both cases the
sensed current creates a ramping voltage across R1, while
the R
/C
filter suppresses noise and transients. R1, R
and
C
should be as physically close to the LM5026 as possible,
and the ground connection from the current sense trans-
former, or R1, should be a dedicated track to the AGND pin.
The current sense components must provide
>
0.5V at the
CS pin when an over-current condition exists.
20147923
FIGURE 12. Start-up Regulator for V
PWR
>
100V
20147924
FIGURE 13. Basic UVLO Configuration
20147925
FIGURE 14. Remote Standby and Disable Control
L
www.national.com
17
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