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PWM Comparator/Slope Compensation
(Continued)
For duty cycles greater than 50 percent, current mode con-
trol circuits are subject to sub-harmonic oscillation. By add-
ing an additional fixed slope voltage ramp signal (slope
compensation) to the current sense signal, this oscillation
can be avoided. The LM5026 integrates this slope compen-
sation by summing a current ramp generated by the oscilla-
tor with the current sense signal. The PWM comparator
ramp signal is a combination of the current waveform at the
CS pin, and an internally generated slope compensation
ramp derived from the oscillator. The internal ramp has an
amplitude of 0 to 45 μAwhich is sourced into an internal 2 k
resistor, plus the external impedance at the CS pin. Addi-
tional slope compensation may be added by increasing the
source impedance of the current sense signal.
Maximum Duty Cycle Clamp
Controlling the maximum duty cycle of an active clamp reset
PWM controller is necessary to limit the voltage stress on the
main and active clamp MOSFETs. The relationship between
the maximum drain-source voltage of the MOSFETs and the
maximum PWM duty cycle is provided by the following equa-
tion:
The main output (OUT_A) duty cycle is normally controlled
by the control current sourced into the COMP pin from the
external feedback circuit. When the feedback demands
maximum output from the converter, the duty cycle will be
limited by one of two circuits within the LM5026: the user
programmable duty cycle clamp and the voltage-dependent
duty cycle limiter, which varies inversely with the input line
voltage.
Programmable Duty Cycle Clamp – The maximum allowed
duty cycle can be programmed by setting a voltage at the
DCL pin to a value less than 2V. The recommended method
to set the DCL pin voltage is with a resistor divider connected
from the RT pin to AGND. The voltage at the RT pin is
internally regulated to 2V, while the current sourced from the
RT pin sets the oscillator frequency. The maximum duty can
be programmed, according to the following equation:
Line Voltage Duty Cycle Limiter - The maximum duty cycle
for the main output driver is also limited by the voltage at the
UVLO pin, which is normally proportional to VIN. The con-
troller outputs are disabled until the UVLO pin voltage ex-
ceeds 1.25V.At the minimum operating voltage (when UVLO
= 1.25V) the maximum duty cycle starts at the duty cycle
clamp level programmed by the DCL pin voltage (80% or
less). As the line voltage increases, the maximum duty cycle
decreases linearly with increasing UVLO voltage, as illus-
trated in
Figure 6
. Ultimately the duty cycle of the main
output is controlled to the least of the following three vari-
ables: the duty cycle controlled by the PWM comparator, the
programmable maximum duty cycle clamp, or the line volt-
age dependent duty cycle limiter.
20147915
FIGURE 4. Opto-coupler to LM5026 COMP Interface
20147916
FIGURE 5. Programming oscillator Frequency and
Maximum Duty Cycle Clamp
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