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參數(shù)資料
| 型號： | LM4935 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | ADC |
| 英文描述： | Audio Sub-System with Dual-Mode Stereo Headphone and Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC |
| 中文描述： | 音頻子系統(tǒng)的雙模單聲道立體聲耳機和揚聲器放大器的高效率和多功能模數(shù)轉換器 |
| 文件頁數(shù)： | 30/112頁 |
| 文件大?。?/td> | 5017K |
| 代理商： | LM4935 |
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12.0 Status & Control Registers
(Continued)
These tables cover the most common applications, obtaining clocks for derivative sample rates such as 22.05 kHz should be
done by increasing the P divider value or using the R/Q dividers.
If the user needs to obtain a clock unrelated to those described above, the following method is advised. An example of obtaining
12.000 MHz from 1.536 MHz is shown below (this is typical for deriving DAC clocks from I2S datastreams).
Choose a small range of P so that the VCO frequency is swept between 40 MHz and 60 MHz. So for P = 3 to 5, sweep the M
inputs from 1 to 3. The most accurate N and N_MOD can be calculated by:
N = FLOOR(((Fout/Fin)*(P*M)),1)
N_MOD = ROUND(32*((((Fout)/Fin)*(P*M)-N),0)
This shows that setting M = 1, N = 39+1/16, P = 5 (i.e. PLL_M = 0, PLL_N = 39, PLL_N_MOD = 2, & PLL_P = 4) gives a
comparison frequency of 1.5 MHz, a VCO frequency of 60 MHz and an output frequency of 12.000 MHz. The same settings can
be used to get 11.025 from 1.4112 MHz for 44.1 kHz sample rates.
Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used but an exact
frequency match cannot be found. The I2S should be master on the LM4935 so that the data source can support appropriate SRC
as required. This method should only be used with data being read on demand to eliminate sample rate mismatch problems.
Where a system clock exists at an integer multiple of the required ADC or DAC clock rate it is preferable to use this rather than
the PLL. The LM4935 is designed to work in 8, 12, 16, 24, 48 kHz modes from a 12 MHz clock and 8, 13, 26, 52 kHz modes from
a 13 MHz clock without the use of the PLL. This saves power and reduces clock jitter which can affect SNR.
The actual ADC and DAC sample rates are set up by the PLL and internal clock dividers.
L
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| LM4936 | Stereo 2W Audio Power Amplifiers with Volume Control and Selectable Control Interface (SPI or I2C) |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LM49350 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High Performance Audio Codec Sub-System with a Ground-Referenced Stereo Headphone Amplifier |
| LM49350RL | 制造商:Texas Instruments 功能描述:Audio Codec 1ADC / 1DAC 36-Pin uSMD T/R 制造商:Texas Instruments 功能描述:AUDIO CODEC SUBSYSTEM 36MICRO SMDXT |
| LM49350RL/NOPB | 功能描述:接口—CODEC Hi Perf Audio Codec Subsystem RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| LM49350RL/NOPB | 制造商:Texas Instruments 功能描述:Audio Codec IC |
| LM49350RLEVAL | 功能描述:音頻 IC 開發(fā)工具 LM49350RL EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
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