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參數資料
| 型號： | LM4550VHX/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 X 1.40 MM, LQFP-48 |
| 文件頁數： | 19/30頁 |
| 文件大?。?/td> | 611K |
| 代理商： | LM4550VHX/NOPB |
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Low Power Modes (Continued)
ticular the startup time of the V
REF circuitry depends on the
value of the decoupling capacitors on pin 27 (3.3 F, 0.1 F
in parallel is recommended).
When the AC Link Digital Interface is powered down the
codec output signals SDATA_IN and BIT_CLK (Primary
mode) are cleared to zero and no control data can be passed
between controller and codec(s). This powerdown state can
be cleared in two ways: Cold Reset (RESET# = 0) or Warm
Reset (SYNC = 1, no BIT_CLK). Cold Reset sets all regis-
ters back to their default values (including clearing PR4)
whereas Warm Reset only clears the PR4 bit and restarts
the AC Link Digital Interface leaving all register contents
otherwise unaffected. For Warm Reset (see Timing Dia-
grams), the SYNC input is used asynchronously. The
LM4550 codec allows the AC Link digital interface power-
down state to be cleared immediately so that its duration can
essentially be as short as T
SH, the Warm Reset pulse width.
However for conformance with AC ’97 Rev 2.1, Warm Reset
should not be applied within 4 frame times of powerdown i.e.
the AC Link powerdown state should be allowed to last at
least 82.8 s.
Improving System Performance
The audio codec is capable of dynamic range performance
in excess of 90 db., but the user must pay careful attention to
several factors to achieve this. A primary consideration is
keeping analog and digital grounds separate, and connect-
ing them together in only one place. Some designers show
the connection as a zero ohm resistor, which allows naming
the nets separately. Although it is possible to use a two layer
board, it is recommended that a minimum of four layers be
used, with the two inside layers being analog ground and
digital ground. If EMI is a system consideration, then as
many as eight layers have been successfully used. The 12
and 25 MHz. clocks can have significant harmonic content
depending on the rise and fall times. With the exception of
the digital VDD pins, (covered later) bypass capacitors
should be very close to the package. The analog VDD pins
should be supplied from a separate regulator to reduce
noise. By operating the digital portion on 3.3V instead of 5V,
an additional 0.5-0.7 db improvement can be obtained.
Depending on power supply layout, routing, and capacitor
ESR, a device instability can occur, resulting in increased
noise on the outputs. This can be eliminated by adding an
inductor in the digital supply line between the supply bypass
capacitors and the DVDD pins, which increases the high
frequency impedance of the supply as seen by the part. This
“current starving” technique slows down internal rise and fall
times, which will improve the signal to noise ratio, especially
at low temperatures. In addition, the EMI radiated from the
board is also reduced.
Multiple Codecs
EXTENDED AC LINK
Up to four codecs can be supported on the extended AC
Link. These multiple codec implementations should run off a
common BIT_CLK generated by the Primary Codec. All
codecs share the AC ’97 Digital Controller output signals,
SYNC, SDATA_OUT, and RESET#. Each codec, however,
supplies its own SDATA_IN signal back to the controller, with
the result that the controller requires one dedicated input pin
per codec (Figure 9).
By definition there can be one Primary Codec and up to
three Secondary Codecs on an extended AC Link. The
Primary Codec has a Codec Identity = (ID1, ID0) = ID = 00
while Secondary Codecs take identities equal to 01, 10 or 11
(see Table 1). The Codec Identity is also used as a chip
select function. This allows the Command and Status regis-
ters in any of the codecs to be individually addressed al-
though the access mechanism for Secondary Codecs differs
slightly from that for a Primary.
The Identity control pins, ID1#, ID0# (pins 46 and 45) are
internally pulled up to DV
DD. The Codec may therefore be
configured as ’Primary’ either by leaving ID1#, ID0# open
(NC) or by strapping them externally to DV
DD (digital supply).
The difference between Primary and Secondary codec
modes is: in their timing source; in the AMAP Slot-to-DAC
mapping used in Output Frames carried by SDATA_OUT;
and in the Tag Bit handling in Output Frames for Command/
Status register access. For a timing source, a Primary codec
divides down by 2 the frequency of the signal on XTAL_IN
and also generates this as the BIT_CLK output for the use of
10097209
FIGURE 8. AC Link Powerdown Timing
LM4550
www.national.com
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