參數(shù)資料
型號(hào)： LM4550VHX/NOPB
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 7 X 7 X 1.40 MM, LQFP-48
文件頁(yè)數(shù)： 18/30頁(yè)
文件大小： 611K
代理商： LM4550VHX/NOPB
Register Descriptions (Continued)
Pin 46
(ID1#)
Pin 45
(ID0#)
D15,28h
(ID1)
D14,28h
(ID0)
Codec Identity
Mode
NC/DV
DD
NC/DV
DD
0
Primary
NC/DV
DD
GND
0
1
Secondary 1
GND
NC/DV
DD
1
0
Secondary 2
GND
1
Secondary 3
EXTENDED AUDIO STATUS/CONTROL REGISTER
(2Ah)
This read/write register provides status and control of the
variable sample rate capabilities in the LM4550. Setting the
LSB of this register to "1" enables Variable Rate Audio (VRA)
mode and allows DAC and ADC sample rates to be pro-
grammed via registers 2Ch and 32h respectively.
BIT
Function
VRA
*0 = VRA off (Frame-rate sampling)
1 = VRA on
Default: 0000h
SAMPLE RATE CONTROL REGISTERS (2Ch, 32h)
These read/write registers are used to set the sample rate
for the left and right channels of the DAC (PCM DAC Rate,
2Ch) and the ADC (PCM ADC Rate, 32h). When Variable
Rate Audio is enabled via bit 0 of the Extended Audio
Control/Status register (2Ah), the sample rates can be pro-
grammed, in 1 Hz increments, to be any value from 4 kHz to
48 kHz. The value required is the hexadecimal representa-
tion of the desired sample rate, e.g. 8000
10 = 1F40h. Below
is a list of the most common sample rates and the corre-
sponding register (hex) values.
Common Sample Rates
SR15:SR0
Sample Rate (Hz)
1F40h
8000
2B11h
11025
3E80h
16000
5622h
22050
AC44h
44100
*BB80h
*48000
CHAIN-IN CONTROL REGISTER (74h)
This read/write register is only needed when using the Chain
In feature. This feature goes beyond the AC ’97 specification
and is not required for standard AC Link operation. The two
LSBs of this register default to the Codec Identity (ID1, ID0)
after reset. This default state corresponds to standard AC
Link operation where the output of codec pin 8 (SDATA_IN)
carries the AC Link Input Frames back to the controller from
the codec.
If the two LSBs differ from the Codec Identity (register 28h
describes the Codec Identity), then the signal present at CIN
(pin 48) is switched through to the SDATA_IN (pin 8) output.
In this fashion, Secondary codecs can be chained together
by connecting one codec’s SDATA_IN pin to the next co-
dec’s CIN pin. This has the end result of only requiring a
single SDATA_IN pin at the controller rather than the stan-
dard one SDATA_IN pin per codec. Note, however, that the
chained codecs time-share the bandwidth of the SDATA_IN
signal under allocation from the controller.
The first codec in the chain (nearest the controller) will have
access to the full bandwith of SDATA_IN following a system
reset (Cold Reset for each codec). To access any other
codec in the chain, the controller must write a suitable value
(i.e. the Identity of the target codec) to the Chain-In Control
register (74h) of each intervening codec in the chain.
The last codec in the serial chain (furthest from the control-
ler) should have its CIN pin connected to digital ground.
When writing software drivers, care should be taken to avoid
any problems that could occur when this last codec in the
chain is set to pass a CIN signal when there is none to pass.
Different controllers may handle an input of all 0s differently
and leaving the CIN pin floating should definitely be avoided.
BIT#
Function
1,0
*(bit1,bit0) = (ID1,ID0): Chain-In off
(bit1,bit0)
≠ (ID1,ID0): Chain-In on
VENDOR ID REGISTERS (7Ch, 7Eh)
These two read-only (4E53h, 4350h) registers contain Na-
tional’s Vendor ID and National’s LM45xx codec version
designation. The first 24 bits (4Eh, 53h, 43h) represent the
three ASCII characters “NSC” which is National’s Vendor ID
for Microsoft’s Plug and Play. The last 8 bits are the two
binary coded decimal characters, 5, 0 and identify the codec
to be an LM4550.
RESERVED REGISTERS
Do not write to reserved registers. In particular, do not write
to registers 24h, 5Ah and 7Ah. All registers not listed in the
LM4550 Register Map are reserved. Reserved registers will
return 0000h if read.
Low Power Modes
The LM4550 provides 7 bits to control the powerdown state
of internal analog and digital subsections and clocks. It also
provides one bit intended to control an external analog
power amplifier. These 8 bits (PR0 – PR6, EAPD) are the 8
MSBs of the Powerdown Control/Status register, 26h. The
status of the four main analog subsections is given by the 4
LSBs in the same register, 26h.
The powerdown bits are implemented in compliance with AC
’97 Rev 2.1 to support the standard device power manage-
ment states D0 – D3 as defined in the ACPI and PCI Bus
Power Management specification.
PR0 controls the powerdown state of the ADC and associ-
ated sampling rate conversion circuitry. PR1 controls power-
down for the DAC and the DAC sampling rate conversion
circuitry. PR2 powers down the mixer circuits (MIX1, MIX2,
National 3D Sound, Mono Out, Line Out). PR3 powers down
V
REF in addition to all the same mixer circuits as PR2. PR4
powers down the AC Link Digital Interface – see Figure 8 for
signal powerdown timing. PR5 disables internal clocks but
leaves the crystal oscillator and BIT_CLK running (needed
for minimum Primary mode powerdown dissipation in multi-
codec systems). PR6 powers down the Headphone ampli-
fier. EAPD controls the External Amplifier PowerDown pin
(pin 47).
After a subsection has undergone a powerdown cycle, the
appropriate status bit(s) in the Powerdown Control/Status
register (26h) must be polled to confirm readiness. In par-
LM4550
www.national.com
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