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參數(shù)資料
| 型號(hào)： | LM2635M/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 350 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | PLASTIC, SOP-20 |
| 文件頁(yè)數(shù)： | 6/13頁(yè) |
| 文件大小： | 734K |
| 代理商： | LM2635M/NOPB |
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Connection Diagram
TOP VIEW
10011903
Plastic SO-20
Order Number LM2635M
See NS Package Number M20B
Pin Descriptions
LSGATE (Pin 1): Gate drive for the low-side N-channel
MOSFET. This signal is interlocked with HSGATE (Pin 20) to
avoid a shoot-through problem.
BOOTV (Pin 2): Power supply for high-side N-channel
MOSFET gate drive. The voltage should be at least one gate
threshold above the converter input voltage to properly op-
erate the high-side N-FET.
PGND (Pin 3): Ground for high current circuitry. It should be
connected to system ground.
SGND (Pin 4): Ground for signal level circuitry. It should be
connected to system ground.
V
CC (Pin 5): Power supply for the controller.
SENSE (Pin 6): Converter output voltage sensing. It pro-
vides input for power good, fast dual comparator control
loop, and over-voltage protection circuitry. It is recom-
mended that a 0.1 F capacitor be connected between this
pin and ground to avoid potential noise problems.
IMAX (Pin 7): Current limit threshold setting. It sinks a fixed
180 A current. By connecting a resistor between the high
side MOSFET drain and this pin, a fixed voltage drop can be
built across the resistor. This voltage drop is compared with
the V
DS of the high-side N-MOSFET to determine if an
over-current condition has occurred.
IFB (Pin 8): High-side N-MOSFET source voltage sensing.
This pin is one V
DS below drain voltage. When this voltage is
lower than that of IMAX pin during the time the high-side FET
is on, it means V
DS is higher than the preset voltage across
the IMAX resistor, which can be interpreted as an over-
current condition.
V
REF (Pin 9): Bandgap reference voltage. This voltage is
mainly for use by other power supplies on the motherboard
which need a reference.
EA_OUT (Pin 10): Output of the error amplifier. The voltage
level on this pin is compared with an internally generated
ramp signal to determine the duty cycle. This pin is neces-
sary for compensating the primary control loop.
FB (Pin 11): Inverting input of the error amplifier. A pin
necessary for compensating the control loop.
FREQ_ADJ (Pin 12): Switching frequency adjustment.
Switching frequency can be adjusted by changing the
grounding resistance on this pin.
PWRGD (Pin 13): Power Good. There are two windows
around the DAC output voltage that are associated with
PWRGD pin, the ±10% window and the ±8% window. If
PWRGD is initially high (open drain state) and output voltage
travels out of ±10% window, PWRGD goes to low (low
impedance to ground). If PWRGD is initially low and output
voltage travels into the ±8% window and has stayed within
the window for at least 10 ms, PWRGD goes to high. A
PWRGD high means the output voltage is at least within the
±10% window whereas a PWRGD low indicates the output
voltage is definitely outside the ±8% window.
VID4:0 (Pins 14, 15, 16, 17, 18): Voltage Identification
Code. The five pins accept an open-ground pattern 5-bit
binary code from outside the chip (typically from the CPU) for
generating the desired output voltage. Each VID pin is inter-
nally pulled up to V
CC via a 90 A current source. Table 1
shows the code table.
OUTEN (Pin 19): Output Enable. The output voltage is
disabled when this pin is pulled low. It is internally pulled up
to V
CC via a 90 A current source.
HSGATE (Pin 20): Gate drive for the high-side N-channel
MOSFET. This signal is interlocked with LSGATE (Pin 1) to
avoid a shoot-through problem.
LM2635
www.national.com
2
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