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參數(shù)資料
| 型號： | LM2240 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | Programmable Timer/Counter |
| 中文描述： | 可編程定時器/計(jì)數(shù)器 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 201K |
| 代理商： | LM2240 |
Circuit Controls
(Continued)
V
CC
e
Pin 16
GND
e
Pin 9
TL/H/10837–9
FIGURE 6. Low Power Operation of Cascaded Timers
Monostable Operation
Precision Timing
In precision timing applications, the LM2240 is used in its
monostable, or self-resetting, mode. The generalized circuit
connection for this application is shown in Figure 3
(S1 closed). The output is normally HIGH and goes LOW
following a trigger input. It remains LOW for the time dura-
tion (T
O
) and then returns to a HIGH state. The duration of
the timing cycle T
O
is given as:
T
O
e
nT
e
NRC
where T
e
RC is the time-base period as set by the choice
of timing components at RC pin 13 (see Performance
Curves) and n is an integer in the range of 1
s
n
s
255 as
determined by the combination of counter outputs (O
0
. . .
O
128
), pins 1 through 8 connected to the output bus.
Counter Output Programming
The binary counter outputs, O
0
. . . O
128
, pins 1 through 8
are open collector type stages and can be shorted together
to a common pull-up resistor to form a wired-OR connec-
tion; the combined output will be LOW as long as any one of
the outputs is LOW The time delays associated with each
counter output can thus be added together. This is done by
simply shorting the outputs together to form a common out-
put bus as shown in Figure 3. For example, if only pin 6 is
connected to the output and the rest left open, the total
duration of the timing cycle, T
O
, is 32T. Similarly, if pins 1, 5,
and 6 are shorted to the output bus, the total time delay is
T
O
e
(1
a
16
a
32) T
e
49T. In this manner, by proper
choice of counter terminals connected to the output bus,
the timing cycle can be programmed to be 1T
s
T
O
s
255T.
Ultra Long Time Delay Application
Two LM2240 units can be cascaded as shown inFigure 7 to
generate extremely long time delays. Total timing cycle of
two cascaded units can be programmed from T
O
e
256 RC
to T
O
e
65,280 RC in 256 discrete steps by selectively
shorting one or more of the counter outputs from Unit 2 to
the output bus. In this application, the reset and the trigger
terminals of both units are tied together and the Unit 2 time
base is disabled. Normally, the output is HIGH when the
system is reset. On triggering, the output goes LOW where it
remains for a total of 256 (255) or 65,280 cycles of the time-
base oscillator.
In cascaded operation, the time-base section of Unit 2 can
be powered down to reduce power consumption by using
the circuit connection of Figure 6. In this case, the V
CC
ter-
minal (pin 16) of Unit 2 is left open, and the second unit is
powered from the regulator output of Unit 1 by connecting
the V
REG
(pin 15) of both units together.
Astable Operation
The LM2240 can be operated in its astable or free running
mode by disconnecting the reset terminal (pin 10) from the
counter outputs. Two typical circuits are shown inFigures 8
and 9. The circuit in Figure 8 operates in its free running
mode with external trigger and reset signals. It starts count-
ing and timing following a trigger input until an external reset
pulse is applied. Upon application of a positive going reset
signal to pin 10, the circuit reverts back to its reset state.
This circuit is essentially the same as that of Figure 3 with
the feedback switch S1 open.
The circuit ofFigure 9 is designed for continuous operation.
It self triggers automatically when the power supply is
turned on, and continues to operate in its free running mode
indefinitely. In astable or free running operation, each of the
counter outputs can be used individually as synchronized
oscillators, or they can be interconnected to generate com-
plex pulse patterns.
7
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