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參數(shù)資料
| 型號： | LM2240 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | Programmable Timer/Counter |
| 中文描述： | 可編程定時器/計數(shù)器 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 201K |
| 代理商： | LM2240 |
Circuit Controls
Counter Outputs (O
0
. . . O
128
, Pins1 thru 8)
The binary counter outputs are buffered open collector type
stages, as shown in the block diagram. Each output is capa-
ble of sinking 2.0 mA at 0.4V V
OL
. In the reset condition, all
the counter outputs are HIGH or in the nonconducting state.
Following a trigger input, the outputs change state in ac-
cordance with the timing diagram of Figure 2. The counter
outputs can be used individually, or can be connected to-
gether in a wired-OR configuration, as described in the pro-
gramming segment of this datasheet.
Reset and Trigger Inputs (R and TRIG, Pins 10 and 11)
The circuit is reset or triggered with positive-going control
pulses applied to pins 10 and 11 respectively. The threshold
level for these controls is approximately two diode drops (
&
1.4V) above ground. Minimum pulse widths for reset and
trigger inputs are shown in the Performance Curves. Once
triggered, the circuit is immune to additional trigger inputs
until the end of the timing cycle.
Modulation and Sync Input (MOD, Pin 12)
The oscillator time-base period (T) can be modulated by
applying a DC voltage to MOD, pin 12 (see Performance
Curves). Also, the time-base oscillator can be synchronized
to an external clock by applying a sync pulse to MOD, pin 12
as shown inFigure 4. Recommended sync pulse widths and
amplitudes are also given.
TL/H/10837–7
FIGURE 4. Operation with External Sync Signal
The time-base can be synchronized by setting the sync
pulse period (T
S
) to be an integer multiple of T. This can be
done by choosing the timing components R and C at pin 13
such that:
T
e
RC
e
(T
S
/m)
where:
m is an integer, 1
s
m
s
10
Figure 5 gives the typical pull-in range for harmonic synchro-
nization for various harmonic modulus, m. For m
k
10, typi-
cal pull-in range is greater than
g
4% of the time-base fre-
quency.
RC Terminal (Pin 13)
The time-base period T is determined by the external RC
network connected to RC, pin 13. When the time-base is
triggered, the waveform at pin 13 is an exponential ramp
with a period T
e
1 RC.
TL/H/10837–8
FIGURE 5. Typical Pull-in Range
for Harmonic Synchronization
Time-Base Output (TBO, Pin 14)
The time-base output is an open-collector type stage as
shown in the block diagram, and requires a 20 k
X
pull-up
resistor to pin 15 for proper circuit operation. In the reset
state, the time-base output is HIGH. After triggering, it pro-
duces a negative-going pulse train with a period T
e
RC, as
shown in the diagram of Figure 2. The time-base output is
internally connected to the binary counter section and can
also serve as the input for the external clock signal when
the circuit is operated with an external time base. The coun-
ter section triggers on the negative-going edge of the timing
or clock pulses generated at TBO, pin 14. The trigger
threshold for the counter section is
&
a
1.4V. The counter
section can be disabled by clamping the voltage level at pin
14 to ground.
When using high supply voltage (V
CC
l
7.0V) and a small
value timing capacitor (C
T
k
0.1
m
F), the pulse width at
TBO pin 14 may be too narrow to trigger the counter sec-
tion. This can be corrected by connecting a 600 pF capaci-
tor from pin 14 to ground.
Regulator Output (V
REG
, Pin 15)
The regulator output V
REG
is used internally to power the
binary counter and the control logic. This terminal can also
be used as a supply to additional LM2240 circuits when
several timer circuits are cascaded (see Figure 6 ) to mini-
mize power dissipation. For circuit operation with an exter-
nal clock, V
REG
can be used as the V
CC
input terminal so
that the internal time-base circuitry is not powered, thus re-
ducing power dissipation. When supply voltages less than
4.5V are used with the internal time-base, pin 15 should be
shorted to pin 16.
6
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