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參數(shù)資料
| 型號： | LM1269NA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 110 MHz I2C Compatible RGB Video Amplifier System with OSD & DACs |
| 中文描述： | 3 CHANNEL, VIDEO PREAMPLIFIER, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 19/20頁 |
| 文件大?。?/td> | 1676K |
| 代理商： | LM1269NA |
DAC Interface Register Definitions
(Continued)
Bit 7
D3–7
Bits 7–0: DAC 3. These eight bits determine the output
voltage of DAC 3.
Bit 0
D3–0
D3–6
D3–5
D3–4
D3–3
D3–2
D3–1
DAC 4 Register (I
2
C address 07h)
Register name: DAC 4 (07h)
Bit 7
D4–7
Bits 7–0: DAC 4. These eight bits determine the output
voltage of DAC 4.
Bit 0
D4–0
D4–6
D4–5
D4–4
D4–3
D4–2
D4–1
DC Offset and OSD Contrast Control Register (I
2
C ad-
dress 08h)
Register name: DC Offset/OSD Cont. (08h)
Bit 7
RSV
Bits 2–0: DC Offset Control. These three bits determine the
active video DC offset to all three channels.
Bits 4–3: OSD Contrast Control. These two bits determine
the contrast level of the OSD information.
Bits 7–5: Reserved.
Bit 0
DC0
RSV
RSV
OSDC1
OSDC0
DC2
DC1
Global Video Control Register (I
2
C address 09h)
Register name: Global Control (09h)
Bit 7
RSV
Bit 0:
Bit 0
BV
RSV
Blank Video. When this bit is a one, blank the
video output. When this bit is a zero allow normal
video out.
Power Save. When this bit is a one, shut down
the analog circuits to support sleep mode. When
this bit is a zero enable the analog circuits for
normal operation.
0
DCF4
DCF1–3
0
PS
Bit 1:
Bit 2:
MUST BE SET TO “0” FOR PROPER OPERA-
TION.
DAC1–3 Configuration. When this bit is a zero
the DAC outputs of DAC1–3 are full scale
(0V–4.5V). When this bit is 1, the range of
DAC1–3 are halved (0V–2.25V).
DAC4 Configuration. When this bit is a zero the
DAC4 output is not mixed with the other DAC
outputs. When the bit is one, 50% of the DAC4
output is added to DAC1–3.
MUST BE SET TO “0” FOR PROPER OPERA-
TION.
Bits 7–6: Reserved.
Bit 3:
Bit 4:
Bit 5:
Increment Mode Register (I
2
C address 0Ah)
Register name: Increment Mode (0Ah)
Bit 7
RSV
Bit 0:
Bit 0
INCR
RSV
RSV
RSV
RSV
RSV
TST
Increment Enable. When set to a “0”, the default
value, the increment mode is enabled. This al-
lows the registers to be updated sequentially by
sending another block of data.
MUST BE SET TO “0” FOR PROPER OPERA-
TION.
Bits 7–2: Reserved.
Bit 1:
Software Reset Register (I
2
C address 0Fh)
Register name: Software Reset (0Fh)
Bit 7
RSV
Bit 0:
Bit 0
SRST
RSV
RSV
RSV
RSV
RSV
RSV
Software Reset. Setting this bit causes a software
reset. All registers (except this one) are loaded
with their default values. All operations currently
in progress are aborted (except for I
2
C transac-
tions). This bit automatically clears itself when the
reset has been completed.
Bits 7–1: Reserved.
L
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