參數(shù)資料
型號(hào): LM12434
廠商: National Semiconductor Corporation
英文描述: Sign Data Acquisition System with Serial I/O and Self-Calibration
中文描述: 注冊(cè)數(shù)據(jù)采集系統(tǒng)的串行I / O和自校準(zhǔn)
文件頁(yè)數(shù): 32/80頁(yè)
文件大小: 1561K
代理商: LM12434
6.0 Operational Information
(Continued)
INSTRUCTION RAM
(Read/Write): (Continued)
Limits
Y
1 & 2
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
l
/
k
Sign
Limit
D7–D0:
Limit: 8-bit limit value.
Sign: Sign of limit value, 0
e
Positive; 1
e
Negative.
l
/
k
: High Limit/Low limit. 0
e
Inputs lower than limit generate interrupt, 1
e
Inputs higher than limit generate
interrupt.
D8:
D9:
D15–D10: Don’t Care.
INTERRUPT ENABLE REGISTER
(Read/Write):
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Number of Conversion
Results in FIFO to
Generate Interrupt (INT2)
Instruction Number
to Generate
Interrupt (INT1)
INT7
X
INT5
INT4
INT3
INT2
INT1
INT0
Bits
Y
0 to 7 enable interrupt generation for the following conditions when the bit is set to 1.
D0:
INT0: Generates an interrupt when a limit is passed in watchdog mode.
D1:
INT1: Generates an interrupt when the sequencer has loaded the instruction number contained in bits D10, D9, and
D8 of the Interrupt Enable register.
D2:
INT2: Generates an interrupt when the number of conversion results in the FIFO is equal to the programmed value
(D15–D11).
D3:
INT3: Generates an interrupt when an auto-zero cycle is completed.
D4:
INT4: Generates an interrupt when a full calibration cycle is completed.
D5:
INT5: Generates an interrupt when a pause condition is encountered.
D6:
This bit is a don’t care condition. No interrupt is associated with this bit.
D7:
INT7: Generates an interrupt when the chip is returned from standby and is ready for operation.
D10–D8: Programmable instruction number used to generate an interrupt when that instruction has been reached.
D15–D11: Programmable number of conversion results in the FIFO to generate an interrupt.
TIMER REGISTER
(Read/Write):
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
N
e
Timer Preset Value
The Timer delays the execution of an instruction if the Timer bit is set in that instruction.
The time delay is:
Delay
e
(32
c
N)
a
2
[
Clock Cycles
]
FIGURE 9. Bit Assignments for LM12434 and LM12
à
L
ó
438 Internal Registers
(Continued)
32
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