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參數(shù)資料
| 型號： | LM12434 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Sign Data Acquisition System with Serial I/O and Self-Calibration |
| 中文描述： | 注冊數(shù)據(jù)采集系統(tǒng)的串行I / O和自校準 |
| 文件頁數(shù)： | 29/80頁 |
| 文件大?。?/td> | 1561K |
| 代理商： | LM12434 |
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6.0 Operational Information
(Continued)
6.2 INTERNAL USER-ACCESSIBLE REGISTERS
Figure 8 shows the LM12434 and LM12
à
L
ó
438 internal user
accessible registers. Figure 9 shows the bit assignment for
each register. All the registers are accessible through the
serial interface bus. Following are the descriptions of the
registers and their bit assignments.
6.2.1 Instruction RAM
The instruction RAM holds up to eight sequentially execut-
able instructions. Each 48-bit long instruction is divided into
three 16-bit sections. READ and WRITE operations can be
issued to each 16-bit section using the instruction’s address
and the 2-bit ‘‘RAM pointer’’ in the Configuration register.
The eight instructions are located at addresses 0000
through 0111. They can be accessed and programmed in
random order.
Read/Write Operations
Any Instruction RAM READ or WRITE can affect the se-
quencer’s operation.
Therefore, the Sequencer should be stopped by setting the
RESET bit to a ‘‘1’’ or by resetting the START bit in the
Configuration Register and waiting for the current instruction
to finish execution before any Instruction RAM READ or
WRITE is initiated.
A soft RESET should be issued by writing a ‘‘1’’ to the Con-
figuration Register’s RESET bit after any READ or WRITE to
the Instruction RAM.
The three sections in the Instruction RAM are selected by
the Configuration Register’s 2-bit ‘‘RAM Pointer’’, bits D8
and D9. The first 16-bit Instruction RAM section is selected
with the RAM Pointer equal to ‘‘00’’. This section can be
programmed for multiplexer channel selection, conversion
resolution, watchdog mode operation, timer or external
SYNC use, pause in instruction and loop bit as described
later. The second 16-bit section holds ‘‘watchdog’’ limit
Y
1,
its sign, and a bit that determines whether an interrupt can
be generated when the input is greater than or less than
limit
Y
1. The third 16-bit section holds ‘‘watchdog’’ limit
Y
2,
its sign, and the ‘‘greater than/less than’’ selection bit.
Instruction RAM, Bank 1, RP
e
00
Bit 0
is the LOOP bit. After an instruction with Bit 0 set to a
‘’1’’ is executed, the sequencer will loop back to instruction
0. The next instruction to be executed will be instruction 0.
Bit 1
is the PAUSE bit. When the PAUSE bit is set (‘‘1’’), the
Sequencer will stop after reading the current instruction.
The instruction will not execute at this point, and the START
bit in the Configuration register will reset to ‘‘0’’. Setting the
PAUSE also causes an interrupt to be issued. The Sequenc-
er is restarted by placing a ‘‘1’’ in the Configuration regis-
ter’s Bit 0 (Start bit).
After the Instruction RAM has been programmed and the
RESET bit is set to ‘‘1’’, the Sequencer retrieves Instruction
0, decodes it, and waits for a ‘‘1’’ to be placed in the Config-
uration register’s START bit. The START bit value of ‘‘1’’
‘‘overrides’’ the action of Instruction 0’s PAUSE bit when
the Sequencer is started. Once started, the Sequencer exe-
cutes Instruction 0 and retrieves, decodes, and executes
each of the remaining instructions. With the PAUSE bit set
to ‘‘1’’ in instruction 0, no PAUSE Interrupt (INT 5) is gener-
ated the first time the Sequencer executes Instruction 0.
When the Sequencer encounters a LOOP bit or completes
all eight instructions, Instruction 0 is retrieved and decoded.
A set PAUSE bit in Instruction 0 now halts the Sequencer
before the instruction is executed. If Pause
e
0, the instruc-
tion loop continues to execute.
Bits 2–4
select which of the eight input channels (IN0–IN7)
will be the non-inverting inputs to the LM12
à
L
ó
438’s ADC.
(See Table III.) They select which of the four input channels
(for IN0–IN3) will be the non-inverting inputs to the
LM12434’s ADC. (See Table IV.)
Bits 5–7
select which of the seven input channels (IN1 to
IN7) will be the inverting inputs to the LM12
à
L
ó
438 ADC.
(See Table III.) They select which of the three input chan-
nels (IN1–IN4) will be the inverting inputs to the LM12434’s
ADC. (See Table IV.) Fully differential operation is created
by selecting two multiplexer channels, one non-inverting
and the other inverting. A code of ‘‘000’’ selects ground as
the inverting input for single ended operation.
Bit 8
is the SYNC bit. Setting Bit 8 to ‘‘1’’ causes the Se-
quencer to hold operation at the internal S/H’s acquisition
cycle and to wait until a rising edge appears at the SYNC
pin. When a rising edge appears, the S/H goes into the
‘‘Hold’’ mode and the ADC begins to perform a conversion
on the next rising edge of CLK. To make the SYNC pin
serve as an input, the Configuration register’s ‘‘SYNC I/O’’
bit (Bit 7) must be set to a ‘‘0’’. With SYNC configured as an
input, it is possible to synchronize the start of a conversion
to external events. When SYNC pin is defined as an output
(SYNC I/O bit
e
1) the SYNC bit in the instruction registers
must not be set to 1.
When the LM12434 and LM12
à
L
ó
438 are used in the
‘‘watchdog’’ mode with external synchronization, two rising
edges on the SYNC input are required to initiate the two
comparisons that are performed during a watchdog instruc-
tion. The first rising edge initiates the comparison of the
selected analog input signal with Limit
Y
1 (found in Instruc-
tion RAM ‘‘01’’) and the second rising edge initiates the
comparison of the same analog input signal with Limit
Y
2
(found in Instruction RAM ‘‘10’’).
Bit 9
is the TIMER bit. When Bit 9 is set to ‘‘1’’, the Se-
quencer will halt until the internal 16-bit Timer counts down
to zero. During this time interval, no ‘‘watchdog’’ compari-
sons or analog-to-digital conversions will be performed.
Bit 10
selects the ADC conversion resolution. Setting Bit 10
to ‘‘1’’ selects 8-bit
a
sign and resetting to ‘‘0’’ selects 12-
bit
a
sign.
Bit 11
is the ‘‘watchdog’’ comparison mode enable bit.
When operating in the ‘‘watchdog’’ comparison mode, the
selected analog input signal is compared with the program-
mable values stored in Limit
Y
1 and Limit
Y
2 (see Instruc-
tion RAM ‘‘01’’ and Instruction RAM ‘‘10’’). Setting Bit 11 to
‘‘1’’ causes two comparisons of the selected analog input
signal, one with each of the two stored limits. When Bit 11 is
reset to ‘‘0’’, an 8-bit
a
sign or 12-bit
a
sign (depending on
the state of Bit 10 of Instruction RAM ‘‘00’’) conversion of
the input signal can take place.
29
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