6.0 Operational Information
(Continued)
CONFIGURATION REGISTER
(Read/Write):
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
Diag.
Test
RAM
Pointer
Sync
I/O
A/Z Each
Cycle
I/S
Stand-
by
Full
Cal
Auto
Zero
Reset
Start
D0:
Start: 0 stops the instruction execution. 1 starts the instruction execution.
D1:
Reset: When set to 1, resets Start bit; also resets all the bits in status registers and resets the instruction pointer to
zero. D1 will then automatically reset itself to zero after 2 clock pulses.
D2:
Auto-Zero: When set to 1 a long (8-cycle) auto-zero calibration cycle is performed.
D3:
Full Calibration: When set to 1 a full calibration cycle (linearity and auto-zero) is performed.
D4:
Standby: When set to 1 the chip goes to low-power standby mode. Resetting the bit will return the chip to active
mode after a short delay.
I/S: Instruction
Y
or extended sign. 0
e
Bits 13–15 of the conversion result hold the instruction number to which the
result belongs; 1
e
Bits 13–15 of the result hold the extended sign bit.
A/Z each Cycle: When set to 1 a short auto-zero cycle is performed before each conversion.
Sync I/O: 0
e
Sync pin is input: 1
e
Sync pin is output.
RAM Pointer: Selects the sections of the instruction RAM, 00
e
Instruction, 01
e
Limits
Y
1, 10
e
Limits
Y
2.
This bit is used for production testing and must be kept zero for normal operation.
Diagnostic: When set to 1, the LM12
à
L
ó
438 will perform a diagnostic conversion along with a properly selected
instruction. This mode is not available on the LM12434.
D5:
D6:
D7:
D9–D8:
D10:
D11:
D15–D12: Don’t Care.
INSTRUCTION RAM
(Read/Write):
Instruction:
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Acquisition Time
Watchdog
8/12
Timer
Sync
MUXIN
b
MUXIN
a
Pause
Loop
D0:
Loop: 0
e
Go to next instruction; 1
e
Loop back to in instruction
Y
0.
Pause: 0
e
No pause; 1
e
Pause; don’t do the instruction. The start bit in the Configuration register resets to 0 when
a pause encountered; a 1 written to the Start bit restarts the instruction execution.
MUXIN
a
: For the LM12
à
L
ó
438, these bits select which input channel is connected to the ADC’s non-inverting input.
For the LM12434, they select which input channel is connected to MUXOUT
a
.
MUXIN
b
: For the LM12
à
L
ó
438, these bits select which input channel is connected to the ADC’s inverting input. For
the LM12434, they select which input channel is connected to MUXOUT
b
.
Sync: 0
e
Normal operation, internal timing, SYNC is an output. 1
e
SYNC is an input; S/H and conversion
(comparison) timing are controlled by an external signal applied to SYNC pin.
Timer: 0
e
Timer is not used for this instruction; 1
e
Instruction execution does not begin until timer counts down to
zero.
8/12: 0
e
12-bit
a
sign resolution. 1
e
8-bit
a
sign resolution.
Watchdog: 0
e
Conventional conversion (no watchdog comparison); 1
e
Instruction performs watchdog compari-
sons.
D1:
D4–D2:
D7–D5:
D8:
D9:
D10:
D11:
D15–D12: Acquisition Time: Determines S/H acquisition time
For 12-bit
a
sign: (9
a
2D) clock cycles. For 8-bit
a
sign: (2
a
2D) clock cycles.
Where D
e
Contents of D15–D12.
For 12-bit
a
sign: Choose D for D
t
0.45 x R
S
[
k
X
]
c
f
CLK
[
MHz
]
.
For
8-bit
a
sign: Choose D for D
t
0.36 x R
S
[
k
X
]
c
f
CLK
[
MHz
]
.
Where R
S
e
Input source resistance.
FIGURE 9. Bit Assignments for LM12434 and LM12
à
L
ó
438 Internal Registers
(Continued)
31