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參數資料
| 型號： | LK4301-7ER |
| 廠商： | POWER-ONE INC |
| 元件分類： | 電源模塊 |
| 英文描述： | 1-OUTPUT 150 W AC-DC PWR FACTOR CORR MODULE |
| 封裝： | HEAT SINK, METAL, CASE K02 |
| 文件頁數： | 16/28頁 |
| 文件大小： | 627K |
| 代理商： | LK4301-7ER |
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BCD20001-G Rev AB
Page 23 of 28
www.power-one.com
K Series with PFC Data Sheet
150 – 280 Watt AC-DC Converters
D Undervoltage Monitor
The input and/or output undervoltage monitoring circuit
operates independently of the built-in input undervoltage
lockout circuit. A logic "low" (JFET output) or "high" signal
(NPN output) is generated at the D output (pin 20), when
one of the monitored voltages drops below the preselected
threshold level Vt. This signal is referenced to Vo– / Vo1–.
The D output recovers, when the monitored voltages
Table 21: Undervoltage monitoring functions
Output type
Monitoring
Minimum adjustment range
Typical hysteresis Vho [% of Vt]
JFET
NPN
Vb 4
Vo1
of threshold level Vt
for Vt min – Vt max
Vtb 4
Vto
Vho
D1
D5
no
yes
-
3.5 – 40 V 1
2.5 – 0.6
D2
D6
yes
no
355 VDC
-
D3
D7
yes
355 VDC
(0.95 – 0.985 Vo1) 2
"0"
D4
D8
no
yes
-
(0.95 – 0.985 Vo1) 2
"0"
D0
D9
no
yes
-
3.5 – 40 V 3
2.5 – 0.6
yes
355 VDC
3.5 – 40 V 3
2.5 – 0.6
DD
yes
355 VDC
3.5 – 40 V 1
2.5 – 0.6
1
Threshold level adjustable by potentiometer
2
Fixed value. Tracking if Vo1 is adjusted via R-input, option P or sense lines.
3
The threshold level permanently adjusted according to customer specification ±2% at 25 °C. Any value within the specified range
is basically possible, but causes a special type designation in addition to the standard option designations (D0/D9).
4
Vb is the voltage generated by the boost regulator. When Vb drops below 355 V, the D signal triggers, and the output(s) will
remain powered during nearly the full hold-up time t h.
exceed Vt + Vh. The threshold level Vbi is adjusted in the
factory. The threshold level Vto is either adjusted by a
potentiometer, accessible through a hole in the front cover,
or adjusted in the factory to a fixed value specified by the
customer.
Option D exists in various versions D0 – DD, as shown in
the table below.
Fig. 37
Option D0 – D4: JFET output, I D
≤ 2.5 mA
NPN output (D5 – DD):
Pin D is internally connected via the collector-emitter path
of a NPN transistor to the negative potential of output 1. VD
< 0.4 V (logic low) corresponds to a monitored voltage level
(Vi and/or Vo1)
> Vt + Vh. The current ID through the open
collector should not exceed 20 mA. The NPN output is not
protected against external overvoltages. VD should not
exceed 40 V.
Vb, Vo1 status
D output, VD
Vb or Vo1
< Vt
high, H, ID
≤ 25 A at VD = 40 V
Vb and Vo1
> Vt + Vh
low, L, VD
≤ 0.4 V at ID = 20 mA
JFET output (D0 – D4):
Pin D is internally connected via the drain-source path of a
JFET (self-conducting type) to the negative potential of
output 1. VD
≤ 0.4 V (logic low) corresponds to a monitored
voltage level (Vi and/or Vo1)
<Vt. The current ID through the
JFET should not exceed 2.5 mA. The JFET is protected by
a
0.5
W
Zener
diode
of
8.2
V
against
external
overvoltages.
Vb, Vo1 status
D output, VD
Vb or Vo1
< Vt
low, L, VD
≤ 0.4 V at ID = 2.5 mA
Vb and Vo1
> Vt + Vh
high, H, ID
≤ 25 A at VD = 5.25 V
Fig. 38
Option D5 – DD: NPN output, Vo1
≤ 40 V, ID
≤ 20 mA
Vo1+
Vo1–
D
VD
ID
Rp
Input
11006
Vo1+
Vo1–
D
VD
ID
Rp
Input
11007
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