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參數(shù)資料
| 型號(hào)： | LH77790B |
| 廠商： | Sharp Corporation |
| 英文描述： | Embedded Microcontroller(32位嵌入式微控制器) |
| 中文描述： | 嵌入式微控制器（32位嵌入式微控制器） |
| 文件頁(yè)數(shù)： | 44/236頁(yè) |
| 文件大?。?/td> | 865K |
| 代理商： | LH77790B |
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Memory & Peripheral Interface
LH77790B User
’
s Guide
5-10
System/User Privileges
Each segment can be individually programmed to give the user and/or the system read and/
or write access to the memory space associated with the segment. This will allow for mem-
ory management and protection. As an example, both code and data can reside in the same
external SRAM with code accessible by the system only and data by the system and the
user. A violation of the programmed privileges will cause an ABORT (data or prefetch).
Write accesses that are aborted are not performed and thus do not corrupt memory.
All memory accesses (Cacheable, Non-cacheable, Local SRAM...) generated by the
LH77790B core will be checked for privilege violation with the exception of two operations,
cache write-back and LCD refresh accesses. During a cache write-back, the memory
access to write the data back to cached memory will not be checked because a check was
performed when the data was originally brought into the cache.
LCD Controller refresh requests are treated as system level requests. However, LCD
requests will not be checked for any privilege violation.
Cacheability
A segment can be cacheable in which case any access to that segment will be handled by
the cache or non-cacheable in which case the access will be handled by the external bus
controller. Since the frame buffer for the LCD is located in main memory, the segment con-
taining the frame buffer should not be cacheable. The external bus controller will ignore
the cacheability bit when it receives an LCD request.
Half-Word Mode (HW)
The ARM7DI core supports only Byte (8-bits) and Word (32-bits) memory accesses. Since
the 790B has a 16-bit data bus, a word access will take two memory accesses. In HW mode,
the 790B allows Half-Word (HW) accesses to the external memory. This means that the
790B will treat all word accesses (read or write) as HW accesses and will take one memory
access. On a word read, the 16-bit data from memory will be sign extended in the external
bus controller and sent to the ARM7DI as a 32-bit word. On a word write, the external bus
controller will write the low order 16-bits of the word from the ARM7DI to external memory.
As mentioned above, the ARM7DI is unaware of HW mode. All LOAD and STORE instruc-
tions are treated as byte or word instructions. For example a LDM instruction will update
the destination address by 4 regardless of the state of HW bit. So LDM and STM will not
operate correctly in HW mode.
Cache does not recognize HW mode. Any memory segment that is operating in HW mode
should be programmed to be non-cacheable to avoid data corruption.
Local SRAM does not recognize HW mode. Local SRAM segment should be programmed
to operate in 32-bit mode (HW = 0).
This mode is very important when it comes to programming x16 Flash memories. Pro-
gramming a x16 Flash memory requires accessing the Flash in a certain sequence that
tells the Flash memory it is getting a command on the data bus instead of data. To program
such a Flash, HW mode should be used.
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