xvii
List of Tables
Pin Descriptions .............................................................................................................2-1
Pinout.............................................................................................................................2-4
Cache Register Offset....................................................................................................4-1
CCR Fields.....................................................................................................................4-2
Cache Status Bits...........................................................................................................4-3
Cache Mapping in SRAM Mode.....................................................................................4-5
Local SRAM Register Offset ..........................................................................................4-6
LSCR Fields...................................................................................................................4-7
Memory Segment Registers...........................................................................................5-3
Bank Configuration Register ..........................................................................................5-4
SDR, START and STOP Association.............................................................................5-7
SDR Fields.....................................................................................................................5-9
BCR0 - BCR5 Fields ....................................................................................................5-11
External SRAM Width ..................................................................................................5-12
BCR6a - BCR7a Fields ................................................................................................5-13
External DRAM Width ..................................................................................................5-13
Activation of CE/CAS and BW .....................................................................................5-14
BCR6b - BCR7b Fields ................................................................................................5-15
DRAM Page Size .........................................................................................................5-17
Address Bus Multiples for x8 DRAMs ..........................................................................5-18
Address Bus Multiples for x16 DRAMs ........................................................................5-19
On-chip (Local) SRAM Memory Cycles .......................................................................5-20
Number of Transfers per Memory Access ...................................................................5-21
Normal Mode DRAM Cycle Parameters ......................................................................5-22
Page Mode DRAM Cycle Parameter ...........................................................................5-22
CPMU Register Offset....................................................................................................6-2
LH77790B Power Modes ...............................................................................................6-3
PCSR Fields...................................................................................................................6-5
UART0 Clock Frequency ...............................................................................................6-6
UART1 Clock Frequency ...............................................................................................6-7
UART2 Clock Frequency ...............................................................................................6-8
Counter/Timer0 Clock Frequency ..................................................................................6-9
Clock/Timer1 Clock Frequency....................................................................................6-10
Counter/Timer2 Clock Frequency ................................................................................6-11
CPU Clock Frequency..................................................................................................6-12
UART External Interface ................................................................................................7-4
UART0 Register Map.....................................................................................................7-4
UART1 Register Map.....................................................................................................7-5
UART2 Register Map.....................................................................................................7-5
Summary of UART Registers.........................................................................................7-6
IER Fields.......................................................................................................................7-7
Interrupt Identification Bit Description ............................................................................7-8
LCR Fields .....................................................................................................................7-9
MCR Fields ..................................................................................................................7-10
LSR Fields....................................................................................................................7-11