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參數(shù)資料
| 型號(hào)： | LH77790B |
| 廠商： | Sharp Corporation |
| 英文描述： | Embedded Microcontroller(32位嵌入式微控制器) |
| 中文描述： | 嵌入式微控制器（32位嵌入式微控制器） |
| 文件頁(yè)數(shù)： | 39/236頁(yè) |
| 文件大?。?/td> | 865K |
| 代理商： | LH77790B |
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LH77790B User
’
s Guide
Memory & Peripheral Interface
5-5
General Operation
The Bus Controller is responsible for controlling all external activities such as:
Memory Interface
Peripheral Interface
DRAM Refresh Requests (Priority 1)
LCD Controller Requests (Priority 2)
Cache External Requests (Priority 3)
ARM7DI External Requests (Priority 4)
The bus controller arbitrates between the various memory requests according to their pri-
orities. The controller treats external peripherals as memory mapped I/O. The controller
supports an external 26-bit address bus and 16-bit data bus. Six multiplexed chip selects/
CAS lines are provided to support six SRAM banks, or four SRAM banks and two DRAM
banks. Each bank has programmable properties to allow interfacing to a wide range of
external memory and peripheral devices. The controller takes care of data alignment
between the 16-bit external data bus and the 32-bit internal data bus and preserves com-
patibility with the ARM. The external bus controller also manages the logical memory
space and maps it to the physical memory space through a memory management scheme.
Memory Management
The ARM7DI can address up to 4GB of address space (32-bit internal address). The 790B
can address up to 64MB externally (26-bit external address). The 790B supports up to
eight programmable segments (0 - 7), a default segment, and six programmable chip
enables. Each segment/chip enable pair can address 64MB of external SRAM or 128MB
of external DRAM. This will give a total of 384MB (6
×
64MB) external SRAM addressable
space or in the case where two of the segments are DRAMs, the total memory addressable
space is 512MB (4
×
64MB SRAM + 2
×
128MB DRAM).
Each of the eight segments consist of 3 registers, a Segment Descriptor Register (SDR),
a START register and a STOP register. The SDR contains information about the system/
user privileges, cacheability, half-word mode, and bank selection. The START and STOP
registers determine the boundaries of the segment. Upon reset, these 3 registers will be
initialized to all 0
’
s for all 8 segments. A Default Segment, segment 8, is used after reset.
The default segment has its own SDR, SDR8, and spans the whole address space
(0: 2
32
- 1) and it uses Bank0 as the default bank. The default segment is used when the
memory address does not match any of the eight main segments. The upper 64KB of the
memory map is reserved for system configuration registers and internal peripheral regis-
ters (see Chapter 19).
The embedded controller supports eight banks, six banks for SRAM and two banks for
DRAM. A SRAM bank will reflect the properties of an external SRAM (or SRAM like
devices) such as chip selects, wait count, and bus width. A DRAM bank will reflect the
properties of an external DRAM such as CAS, RAS, bank size, page mode, wait count,
and bus width.
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