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參數(shù)資料
| 型號： | LH543620 |
| 廠商： | Sharp Corporation |
| 英文描述： | 1024 x 36 Synchronous FIFO |
| 中文描述： | 1024 × 36同步FIFO |
| 文件頁數(shù)： | 14/38頁 |
| 文件大小： | 269K |
| 代理商： | LH543620 |
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Byte-Order-Reversal and Bus Funneling/
Defunneling Functions
Word width can be selected at the Input Port and/or
the Output Port to be 36, 18 or 9 bits wide. When the
Output Port width is selected to be 36 bits, it is possible
to select Byte-Order-Reversal.
The funneling mechanism is controlled by the inputs
WSI[1:0] and WSO[1:0] according to Tables 2 and 5. Data
is packed and unpacked from a 36-bit word memory array.
Table 7 describes all combinations of funneling/defunneling.
Changes to the funneling/defunneling settings during
system operation should be made one clock before a
word boundary, as shown in Example 3.
Example 1: 36-to-9 Funneling
CONDITIONS
WSI[1:0]
3
RESULTS
WSO[1:0]
–
Input 36 bits wide.
Output 9 bits wide.
Pins used are Q[8:0].
–
0
The dataflow structure is illustrated by Figure 5.
Example 2: 18-to-36 Defunneling With Byte Reversal
This example performs two functions:
1.
Bus width change
2.
Big Endian to Little Endian conversion
This configuration can be used for connecting the Intel
80286 to the Motorola 68040.
CONDITIONS
WSI[1:0]
RESULTS
WSO[1:0]
1
–
Input 18 bits wide.
Pins used are D[17:0].
Output 36 bits wide with byte
order reversal.
–
2
The dataflow structure is illustrated by Figure 6.
Example 3: Changing Input Bus Width From 9 to 36
During Operation
CKI
0
1
2
3
4
WSI
0
0
0
3
3
ACTION
Write 1st 9-bit byte
Write 2nd 9-bit byte
Write 3rd 9-bit byte
Write 4th 9-bit byte
Write 1st 36-bit word
Table 7. Bus Funneling/Defunneling *
INPUT
OUTPUT
CKI
cycles
0
1
2
3
4
5
6
7
8
WSI = 0
D[35:9]
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
WSI = 1
D[35:18]
xx
xx
xx
xx
xx
WSI = 3
D[35:0]
B3
B2
B7
B6
CKO
cycles
0
1
2
3
4
5
6
7
8
WSO = 3
Q[35:0]
B2
B6
WSO = 2
Q[35:0]
B1
B5
WSO = 1
WSO = 0
Q[35:9]
B2
B3
B0
B1
B6
D[8:0]
B0
B1
B2
B3
B4
B5
B6
B7
B8
Q[35:18]
B3
B1
B7
B5
Q[17:0]
B1
B3
B5
B7
Q[8:0]
B0
B1
B2
B3
B4
B3
B7
B1
B5
B0
B4
B0
B4
B2
B6
B3
B7
B2
B0
B6
B4
B0
B2
B4
B6
B3
B0
B1
B2
B7
B1
B2
B3
B0
B5
WSO = 3
Q[35:0]
B2
B6
WSO = 2
Q[35:0]
B1
B5
WSO = 1
WSO = 0
Q[35:9]
B2
B3
B0
B1
B6
WSO = 0
Q[35:9]
B2
B3
B0
B1
B6
D[17:0]
B1
B3
B5
B7
B9
Q[35:18]
B3
B1
B7
B5
Q[17:0]
B1
B3
B5
B7
Q[8:0]
B0
B1
B2
B3
B4
0
1
2
3
4
B0
B2
B4
B6
B8
0
1
2
3
4
B3
B7
B1
B5
B0
B4
B0
B4
B2
B6
B3
B7
B2
B0
B6
B4
B0
B2
B4
B6
B3
B0
B1
B2
B7
B1
B2
B3
B0
B5
WSO = 3
Q[35:0]
B2
B6
WSO = 2
Q[35:0]
B1
B5
WSO = 1
Q[35:18]
B3
B1
B7
B5
Q[17:0]
B1
B3
B5
B7
Q[8:0]
B0
B1
B2
B3
B4
0
1
B1
B5
B0
B4
0
1
B3
B7
B1
B5
B0
B4
B0
B4
B2
B6
B3
B7
B2
B0
B6
B4
B0
B2
B4
B6
B3
B0
B1
B2
B7
B1
B2
B3
B0
B5
*
NOTE:
B0, B1, . . ., represent data bytes.
LH543620
1024
×
36 Synchronous FIFO
14
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