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參數(shù)資料
| 型號(hào)： | LH540203 |
| 廠商： | Sharp Corporation |
| 英文描述： | CMOS 2048 x 9 Asynchronous FIFO |
| 中文描述： | 2048 × 9的CMOS異步FIFO |
| 文件頁(yè)數(shù)： | 1/17頁(yè) |
| 文件大?。?/td> | 153K |
| 代理商： | LH540203 |
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LH540203
CMOS 2048
×
9 Asynchronous FIFO
FEATURES
Fast Access Times: 15/20/25/35/50 ns
Fast-Fall-Through Time Architecture Based on
CMOS Dual-Port SRAM Technology
Input Port and Output Port Have Entirely
Independent Timing
Expandable in Width and Depth
Full, Half-Full, and Empty Status Flags
Data Retransmission Capability
TTL-Compatible I/O
Pin and Functionally Compatible with Sharp LH5498
and with Am/IDT/MS7203
Control Signals Assertive-LOW for Noise Immunity
Packages:
28-Pin, 300-mil PDIP
28-Pin, 300-mil SOJ *
32-Pin PLCC
PIN CONNECTIONS
FUNCTIONAL DESCRIPTION
The LH540203 is a FIFO (First-In, First-Out) memory
device, based on fully-static CMOS dual-port SRAM tech-
nology, capable of storing up to 2048 nine-bit words. It
follows the industry-standard architecture and package
pinouts for nine-bit asynchronous FIFOs. Each nine-bit
LH540203 word may consist of a standard eight-bit byte,
together with a parity bit or a block-marking/framing bit.
The input and output ports operate entirely inde-
pendently of each other, unless the LH540203 becomes
either totally full or else totally empty. Data flow at a port
is initiated by asserting either of two asynchronous, as-
sertive-LOW control inputs: Write (W) for data entry at the
input port, or Read (R) for data retrieval at the output port.
Full, Half-Full, and Empty status flags monitor the
extent to which the internal memory has been filled. The
system may make use of these status outputs to avoid
the risk of data loss, which otherwise might occur either
by attempting to write additional words into an already-full
LH540203, or by attempting to read additional words from
an already-empty LH540203. When an LH540203 is
operating in a depth-cascaded configuration, the Half-Full
Flag is not available.
540203-2D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
W
D
8
D
3
D
2
D
1
D
0
XI
FF
Q
0
Q
1
Q
2
Q
3
Q
8
V
SS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D
7
FL/RT
RS
EF
XO/HF
Q
5
Q
4
R
Q
6
Q
7
D
6
D
5
D
4
V
CC
28-PIN PDIP
28-PIN SOJ
*
TOP VIEW
Figure 1. Pin Connections for PDIP and
SOJ * Packages
5
6
7
8
9
10
D
2
D
1
D
0
XI
FF
11
2
3
4
32 31 30
29
28
27
26
25
24
NC
EF
D
3
D
8
W
N
*
V
C
D
4
D
5
14 15 16
20
19
18
17
FL/RT
RS
23
XO/HF
22
21
12
13
NC
Q
2
1
Q
3
Q
8
V
S
N
*
R
Q
4
Q
5
540203-3D
Q
0
Q
1
D
6
D
7
Q
7
Q
6
32-PIN PLCC
TOP VIEW
NOTE:
*
= No external electrical connections are allowed.
Figure 2. Pin Connections for PLCC Package
* This is a final data sheet; except that all references to the SOJ package have Advance Information status.
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LH540204 | CMOS 4096 x 9 Asynchronous FIFO |
| LH540205 | CMOS 8192 x 9 Asynchronous FIFO |
| LH540215 | 512 x 18 / 1024 x 18 Synchronous FIFO |
| LH540235 | 2048 x 18 / 4096 x 18 Synchronous FIFOs |
| LH5420 | 256 x 36 x 2 Bidirectional FIFO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH540203-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Asynchronous FIFO |
| LH540203-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Asynchronous FIFO |
| LH540203-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Asynchronous FIFO |
| LH540203-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Asynchronous FIFO |
| LH540203-50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Asynchronous FIFO |
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