參數(shù)資料
型號(hào)： LH28F640SP
廠商： Sharp Corporation
英文描述： 64Mbit (4Mbitx16/8Mbitx8) Page Flash Memory
中文描述： 64兆比特（4Mbitx16/8Mbitx8）頁(yè)閃存
文件頁(yè)數(shù)： 28/45頁(yè)
文件大?。?/td> 1041K
代理商： LH28F640SP
LHF64P01 26
t
PLPH
t
PLPH
t
2VPH
t
PLRH
t
PHQV
t
PHQV
(A) Reset during Read Array Mode
(B) Reset during Erase or Program Mode
(C) RP# rising timing
RP#
RP#
V
IL
V
IH
V
IL
V
IH
V
CC
GND
V
CC
(min)
RP#
V
IL
V
IH
SR.7="1"
V
OH
V
OL
(D/Q)
DQ
15-0
VALID
OUTPUT
High Z
(P)
(P)
(P)
V
OH
V
OL
(D/Q)
DQ
15-0
VALID
OUTPUT
High Z
V
OH
V
OL
(D/Q)
DQ
15-0
VALID
OUTPUT
High Z
t
PHQV
t
VHQV
ABORT
COMPLETE
NOTES:
1. A reset time, t
PHQV
, is required from the later of SR.7 (STS) going "1" (High Z) or RP# going high until outputs are valid.
Refer to AC Characteristics - Read-Only Operations for t
PHQV
.
2. The device may reset if t
PLPH
is <100ns, but this is not guaranteed.
3. Sampled, not 100% tested.
4. If RP# asserted while a block erase, (page buffer) program, block lock configuration or OTP program operation is not
executing, the reset will complete within 100ns.
5. When the device power-up, holding RP# low minimum 100ns is required after V
CC
has been in predefined range and also
has been in stable there.
Reset AC Specifications (V
CC
=2.7V-3.6V, T
A
=-40
°
C to +85
°
C)
Symbol
Parameter
Notes
Min.
Max.
Unit
t
PLPH
RP# Low to Reset during Read
(RP# must be low during power-up.)
1, 2, 3
100
ns
t
PLRH
t
2VPH
t
VHQV
RP# Low to Reset during Erase or Program
1, 3, 4
30
μ
s
V
CC
2.7V to RP# High
V
CC
2.7V to Output Delay
1, 3, 5
100
ns
3
1
ms
Figure 10. AC Waveform for Reset Operations
Rev. 0.06
1.2.6 Reset Operations
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