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| 型號： | LH28F640SP |
| 廠商： | Sharp Corporation |
| 英文描述： | 64Mbit (4Mbitx16/8Mbitx8) Page Flash Memory |
| 中文描述： | 64兆比特（4Mbitx16/8Mbitx8）頁閃存 |
| 文件頁數(shù)： | 26/45頁 |
| 文件大?。?/td> | 1041K |
| 代理商： | LH28F640SP |
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LHF64P01 24
Rev. 0.06
1.2.5 AC Characteristics - Write Operations
(1), (2)
NOTES:
1. The timing characteristics for reading the status register during block erase, (page buffer) program, block lock
configuration and OTP program operations are the same as during read-only operations. Refer to AC Characteristics for
read-only operations.
2. A write operation can be initiated and terminated with either CE
0
, CE
1
, CE
2
or WE#.
3. Sampled, not 100% tested.
4. Write pulse width low (t
WP
) is defined from the first edge of CE
0
, CE
1
or CE
2
that enables the device or the falling edge
of WE# (whichever occurs last) to the first edge of CE
0
, CE
1
or CE
2
that disables the device or the rising edge of WE#
(whichever occurs first). Hence, t
WP
=t
WLWH
=t
ELEH
=t
WLEH
=t
ELWH
.
5. Write pulse width high (t
WPH
) is defined from the first edge of CE
0
, CE
1
or CE
2
that disables the device or the rising edge
of WE# (whichever occurs first) to the first edge of CE
0
, CE
1
or CE
2
that enables the device or the falling edge of WE#
(whichever occurs last). Hence, t
WPH
=t
WHWL
=t
EHEL
=t
WHEL
=t
EHWL
.
6. V
PEN
should be held at V
PEN
=V
PENH
until determination of block erase, (page buffer) program, block lock configuration
or OTP program success (SR.1/3/4/5=0).
7. Refer to Table 5 for valid address and data for block erase, (page buffer) program, block lock configuration and OTP
program.
8. The output delay time t
AVQV
or t
ELQV
is required in addition to t
WHGL
(t
EHGL
) for read operations after command writes.
9. The timing is defined from the first edge of CE
0
, CE
1
or CE
2
that enables the device.
10. The timing is defined from the first edge of CE
0
, CE
1
or CE
2
that disables the device.
11. STS timings depend on STS configuration.
V
CC
=2.7V-3.6V, T
A
=-40
°
C to +85
°
C
Symbol
Parameter
Notes
Min.
Max.
Unit
t
AVAV
t
PHWL
(t
PHEL
)
t
ELWL
(t
WLEL
)
t
WLWH
(t
ELEH
)
t
DVWH
(t
DVEH
)
t
AVWH
(t
AVEH
)
t
WHEH
(t
EHWH
)
t
WHDX
(t
EHDX
)
t
WHAX
(t
EHAX
)
t
WHWL
(t
EHEL
)
t
VVWH
(t
VVEH
)
t
WHGL
(t
EHGL
)
t
WHR0
(t
EHR0
)
t
WHRL
(t
EHRL
)
t
QVVL
t
FLWH
/t
FHWH
(t
FLEH
/t
FHEH
)
t
WHFL
/t
WHFH
(t
EHFL
/t
EHFH
)
Write Cycle Time
120
ns
RP# High Recovery to WE# (
CE
X
) Going Low
CE
X
(WE#) Setup to WE# (CE
X
) Going Low
WE# (CE
X
) Pulse Width Low
Data Setup to WE# (CE
X
) Going High
Address Setup to WE# (CE
X
) Going High
CE
X
(WE#) Hold from WE# (CE
X
) High
Data Hold from WE# (CE
X
) High
Address Hold from WE# (CE
X
) High
WE# (CE
X
) Pulse Width High
V
PEN
Setup to WE# (CE
X
) Going High
3, 9
1
μ
s
9
0
ns
4, 9, 10
70
ns
7, 10
50
ns
7, 10
55
ns
10
0
ns
10
0
ns
10
0
ns
5, 9, 10
30
ns
3, 10
0
ns
Write Recovery before Read
8
35
ns
WE# (CE
X
) High to SR.7 Going "0", STS Going Low
10, 11
500
ns
V
PEN
Hold from Valid SRD, STS High Z
3, 6, 11
0
ns
BYTE# Setup to WE# (CE
X
) Going High
10
50
ns
BYTE# Hold from WE# (CE
X
) High
10
90
ns
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