參數(shù)資料
型號: LH28F400SUN
廠商: Sharp Corporation
英文描述: 4Mbit(512Kbit x 8,256Kbit x 16) 3.3V Flash Memory
中文描述: 的4Mb(512Kbit x 8256千位× 16)3.3閃存
文件頁數(shù): 11/35頁
文件大?。?/td> 294K
代理商: LH28F400SUN
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SU-NC
11
Figure 7. Block Erase with Compatible Status Register
28F400SUT-NC60-5
START
BUS
OPERATION
COMMAND
COMMENTS
WRITE 20H
WRITE D0H AND
BLOCK ADDRESS
CSR.7 =
0
NO
YES
1
0
1
0
1
CSR FULL STATUS
CHECK IF DESIRED
OPERATION
COMPLETE
CLEAR CSRD
RETRY/ERROR
RECOVERY
(NOTE)
ERASE
SUCCESSFUL
V
LOW
DETECT
READ CSRD
(see above)
SUSPEND
ERASE
SUSPEND
ERASE LOOP
CSR.4, 5 =
CSR.3 =
Write
Write
Read
Standby
Block Erase
Confirm
D = 20H
A = X
D = D0H
A = BA
Q = CSRD
Toggle CE or OE
to update CSRD.
A = X
Repeat for subsequent Block Erasures.
CSR Full Status Check can be done after each Block Erase,
or after a sequence of Block Erasures.
Write FFH after the last operation to reset
device to read array mode.
See Command Bus Cycle notes for description of codes.
Check CSR.7
1 = WSM Ready
0 = WSM Busy
BUS
OPERATION
COMMAND
CSR FULL STATUS CHECK PROCEDURE
COMMENTS
Standby
Standby
Check CSR.4, 5
1 = Erase Error
0 = Erase Successful
Both 1 = Command
Sequence Error
CSR.3, 4, 5 should be cleared, if set, before further attempts
are initiated.
NOTE:
If CSR.3 (VPPS) is set to '1', after clearing CSR.3/4/5,
1. Issue Reset WP command.
2. Retry Single Block Erase command.
3. Set WP command is issued, if necessary.
If CSR.3 (VPPS) is set to '0', after clearing CSR.3/4/5,
1. Retry Single Block Erase command.
If power is off or RP is low during erase operation,
1. Clear CSR.3/4/5 and issue Reset WP command,
2. Retry Single Block Erase command.
3. Set WP command is issued, if necessary.
READ COMPATIBLE
STATUS REGISTER
Check CSR.3
1 = V
PP
Low Detect
0 = V
PP
OK
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