參數(shù)資料
型號(hào): LH28F320BFHE-PBTL60
廠商: Sharp Corporation
英文描述: 32M (x16) Flash Memory
中文描述: 32M的(x16)的快閃記憶體
文件頁(yè)數(shù): 29/37頁(yè)
文件大?。?/td> 693K
代理商: LH28F320BFHE-PBTL60
LHF32FB4 27
ABORT
COMPLETE
t
PLPH
t
PLPH
t
2VPH
t
PLRH
t
PHQV
t
PHQV
(A) Reset during Read Array Mode
(B) Reset during Erase or Program Mode
(C) RST# rising timing
RST#
RST#
V
IL
V
IH
V
IL
V
IH
V
CC
GND
V
CC
(min)
RST#
V
IL
V
IH
SR.7="1"
V
OH
V
OL
(D/Q)
DQ
15-0
VALID
OUTPUT
High Z
(P)
(P)
(P)
V
OH
V
OL
(D/Q)
DQ
15-0
VALID
OUTPUT
High Z
V
OH
V
OL
(D/Q)
DQ
15-0
VALID
OUTPUT
High Z
t
PHQV
t
VHQV
NOTES:
1. A reset time, t
PHQV
, is required from the later of SR.7 (RY/BY#) going "1" (High Z) or RST# going high until outputs are
valid. Refer to AC Characteristics - Read-Only Operations for t
PHQV
.
2. t
PLPH
is <100ns the device may still reset but this is not guaranteed.
3. Sampled, not 100% tested.
4. If RST# asserted while a block erase, full chip erase, (page buffer) program or OTP program operation is not executing,
the reset will complete within 100ns.
5. When the device power-up, holding RST# low minimum 100ns is required after V
CC
has been in predefined range and
also has been in stable there.
Reset AC Specifications (V
CC
=2.7V-3.6V, T
A
=-40
°
C to +85
°
C)
Symbol
Parameter
Notes
Min.
Max.
Unit
t
PLPH
RST# Low to Reset during Read
(RST# should be low during power-up.)
1, 2, 3
100
ns
t
PLRH
t
2VPH
t
VHQV
RST# Low to Reset during Erase or Program
1, 3, 4
22
μ
s
V
CC
2.7V to RST# High
V
CC
2.7V to Output Delay
1, 3, 5
100
ns
3
1
ms
Figure 11. AC Waveform for Reset Operations
Rev. 2.44
1.2.6 Reset Operations
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