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參數(shù)資料
| 型號： | LH28F040SUTD-Z4 |
| 廠商： | Sharp Corporation |
| 英文描述： | 4M (512K 】 8) Flash Memory |
| 中文描述： | 4分（為512k】8）閃存 |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 247K |
| 代理商： | LH28F040SUTD-Z4 |
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LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
16
Figure 10. Bank Erase All Unlocked Blocks with Compatible Status Registers
START
(NOTE)
BUS
OPERATION
COMMAND
COMMENTS
WRITE A7H
CSR.7 =
0
YES
NO
1
0
1
0
1
CSR FULL STATUS
CHECK IF DESIRED
OPERATION
COMPLETE
WRITE D0H
CLEAR CSRD
RETRY/ERROR
RECOVERY
(NOTE)
ERASE
SUCCESSFUL
V
LOW
DETECT
READ CSRD
(see above)
SUSPEND
ERASE
SUSPEND
ERASE LOOP
CSR.4, 5 =
CSR.3 =
Write
Write
Read
Standby
Erase All
Unlocked
Blocks
Confirm
D = A7H
A = X
D = D0H
A = X
Q = CSRD
Toggle
BE
, BE
1
or OE
to update CSRD.
A = X
CSR Full Status Check can be done after Erase All Unlocked
Block, or after a sequence of Erasures.
Write FFH after the last operation to reset
device to read array mode.
See Command Bus Cycle notes for description of codes.
NOTE:
Where power off or reset during erase operation,
1. Clear CSR.3/4/5 and issue Reset WP command,
2. Retry Erase All Unlocked Block Erase command to
erase all blocks, or issue Single Block Erase to
erase all of the unlocked blocks in sequence.
3. Set WP command is issued, if necessary.
Check CSR.7
1 = WSM Ready
0 = WSM Busy
BUS
OPERATION
COMMAND
CSR FULL STATUS CHECK PROCEDURE
COMMENTS
Standby
Standby
Check CSR.4, 5
1 = Erase Error
0 = Erase Successful
Both 1 = Command
Sequence Error
CSR.3, 4, 5 should be cleared, if set, before further attempts
are initiated.
NOTE:
If CSR.3 (VPPS) is set to '1', after clearing CSR.3/4/5,
1. Issue Reset WP command,
2. Retry Erase All Unlocked Block Erase command to erase
all blocks, or issue Single Block Erase to erase all of the
unlocked blocks in sequence.
3. Set WP command is issued, if necessary.
If CSR.3 (VPPS) is set to '0', after clearing CSR.3/4/5,
1. Retry Erase All Unlocked Block Erase command.
28F040SUZ4-10
READ COMPATIBLE
STATUS REGISTER
Check CSR.3
1 = V
PP
Low Detect
0 = V
PP
OK
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