參數(shù)資料
型號: LH28F016SANS-70
廠商: Sharp Corporation
英文描述: 16 Mbit(1 Mbit x 16, 2 Mbit x 8)
中文描述: 16兆位(1兆位× 16,2兆位× 8)
文件頁數(shù): 29/37頁
文件大小: 326K
代理商: LH28F016SANS-70
16M (1M × 16, 2M × 8) Flash Memory
LH28F016SU
29
AC Characteristics for WE
- Controlled Command Write Operations
1
(Continued)
T
A
= 0°C to +70°C
NOTES:
CE
is defined as the latter of CE
0
or CE
1
going Low or the first of CE
0
or CE
1
going High.
1. Read timing during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Write/Erase durations are measured to valid Status Register (CSR) Data.
5. Word/Byte write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of WE
for all Command Write Operations.
SYMBOL
PARAMETER
V
CC
= 5.0 ± 0.25 V
V
CC
= 5.0 ± 0.5 V
UNITS
NOTE
TYP.
MIN.
MAX.
TYP.
MIN.
MAX.
t
AVAV
Write Cycle Time
70
80
ns
t
VPWH
V
PP
Setup to WE Going High
100
100
ns
3
t
PHEL
RP
Setup to CE
Going Low
480
480
ns
t
ELWL
CE
Setup to WE Going Low
0
0
ns
t
AVWH
Address Setup to WE Going High
50
50
ns
2, 6
t
DVWH
Data Setup to WE Going High
50
50
ns
2, 6
t
WLWH
WE Pulse Width
40
50
ns
t
WHDX
Data Hold from WE High
0
10
ns
2
t
WHAX
Address Hold from WE High
10
10
ns
2
t
WHEH
CE
Hold from WE High
10
10
ns
t
WHWL
WE Pulse Width High
30
30
ns
t
GHWL
Read Recovery before Write
0
0
ns
t
WHRL
WE High to RY
/BY
Going Low
100
100
ns
t
RHPL
RP
Hold from Valid Status Register
(CSR, GSR, BSR) Data and
RY
/BY
High
0
0
ns
3
t
PHWL
RP
High Recovery to WE Going Low
1
1
μs
t
WHGL
Write Recovery before Read
60
65
ns
t
QVVL
V
PP
Hold from Valid Status Register
(CSR, GSR, BSR) Data and
RY
/BY
High
0
0
μs
t
WHQV1
t
WHQV2
Duration of Word/Byte Write Operation
8
4.5
8
4.5
μs
4, 5
Duration of Block Erase Operation
0.3
0.3
s
4
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