參數(shù)資料
型號(hào)： LFX125C-3F900I
廠(chǎng)商： Lattice Semiconductor Corporation
英文描述： The ispXPGA architecture
中文描述： 在ispXPGA架構(gòu)
文件頁(yè)數(shù)： 38/89頁(yè)
文件大?。?/td> 941K
代理商： LFX125C-3F900I
Lattice Semiconductor
ispXPGA Family Data Sheet
38
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Units
t
PWH
t
PWL
t
R
, t
F
t
INSTB
f
MDIVIN
f
MDIVOUT
f
NDIVIN
f
NDIVOUT
f
VDIVIN
f
VDIVOUT
t
OUTDUTY
Input clock, high time
80% to 80%
1.2
—
ns
Input clock, low time
20% to 20%
1.2
—
ns
Input Clock, rise and fall time
20% to 80%
—
3.0
ns
Input clock stability, cycle to cycle (peak)
—
+/- 250
ps
M Divider input, frequency range
10
320
MHz
M Divider output, frequency range
10
320
MHz
N Divider input, frequency range
10
320
MHz
N Divider output, frequency range
10
320
MHz
V Divider input, frequency range
100
400
MHz
V Divider output, frequency range
10
320
MHz
output clock, duty cycle
40
60
%
t
JIT(CC)
Output clock, cycle to cycle jitter (peak)
Clean reference.
10 MHz < f
MDIVOUT
< 20 MHz or
100MHz < f
VDIVIN
< 160 MHz
Clean reference.
20 MHz < f
MDIVOUT
< 320 MHz and
160MHz < f
VDIVIN
< 320 MHz
Clean reference.
10 MHz < f
MDIVOUT
< 20 MHz or
100MHz < f
VDIVIN
< 160 MHz
Clean reference.
20 MHz < f
MDIVOUT
< 320 MHz and
160MHz < f
VDIVIN
< 320 MHz
Internal feedback
—
+/- 250
ps
—
+/- 150
ps
T
JIT(PERIOD)
Output clock, period jitter (peak)
—
+/- 300
ps
—
+/- 150
ps
t
CLK_OUT_DELAY
Input clock to CLK_OUT delay
t
PHASE
Input clock to external feedback delta
t
LOCK
Time to acquire phase lock after input stable
t
PLL_DELAY
Delay increment (Lead/Lag)
t
RANGE
Total output delay range (lead/lag)
t
PLL_RSTW
Minimum reset pulse width
t
CLK_IN
Global clock input delay
t
PLL_SEC_DELAY
Secondary PLL output delay (t
PLL_DELAY
)
1. This condition assures that the output phase jitter will remain within speci
fi
cation
2. Accumulated jitter measured over 10,000 waveform samples
3. Internal timing for reference only.
—
3.0
ns
External feedback
—
600
ps
—
25
us
Typical = +/- 250ps
+/- 120 +/- 550
ps
+/- 0.84 +/- 3.85
ns
—
1.8
ns
3
—
1.0
ns
—
1.5
ns
相關(guān)PDF資料
PDF描述
LFX125C-4F900I The ispXPGA architecture
LFX200B-3F900I The ispXPGA architecture
LFX1200B-03F900C The ispXPGA architecture
LFX200C-3F900C The ispXPGA architecture
LFX200C-3F900I The ispXPGA architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFX125C-3FE680C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:ispXPGA Family
LFX125C-3FE680I 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:ispXPGA Family
LFX125C-3FH516C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:ispXPGA Family
LFX125C-3FH516I 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:ispXPGA Family
LFX125C-3FN256C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:ispXPGA Family
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*