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參數(shù)資料
| 型號： | LFECP15E-5F484C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | 12-Bit 66 kSPS ADC Ser. Out, Pgrmable MSB/LSB First, Pgrmable Power Down/Output Data Length, 11 Ch. 20-PLCC |
| 中文描述： | FPGA, 1920 CLBS, 15400 GATES, 420 MHz, PBGA484 |
| 封裝： | 23 X 23 MM, FPBGA-484 |
| 文件頁數(shù)： | 17/117頁 |
| 文件大?。?/td> | 557K |
| 代理商： | LFECP15E-5F484C |
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2-14
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-16. Memory Core Reset
For further information on sysMEM EBR block, please see the details of additional technical documentation at the
end of this data sheet.
sysDSP Block
The LatticeECP-DSP family provides a sysDSP block making it ideally suited for low cost, high performance Digital
Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response
(FIR)
fi
lters; Fast Fourier Transforms (FFT) functions, correlators, Reed-Solomon/Turbo/Convolution encoders and
decoders. These complex signal processing functions use similar building blocks such as multiply-adders and mul-
tiply-accumulators.
sysDSP Block Approach Compare to General DSP
Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with
fi
xed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by
higher clock speeds. The LatticeECP, on the other hand, has many DSP blocks that support different data-widths.
This allows the designer to use highly parallel implementations of DSP functions. The designer can optimize the
DSP performance vs. area by choosing appropriate level of parallelism. Figure 2-17 compares the serial and the
parallel implementations.
Q
SET
D
L
CLR
Output Data
Latches
Q
D
Memory Core
Port A[17:0]
SET
Port B[17:0]
RSTB
GSRN
Programmable Disable
RSTA
L
CLR
相關PDF資料 |
PDF描述 |
|---|---|
| LFECP15E-5F484I | LatticeECP/EC Family Data Sheet |
| LFECP15E-5F672I | LatticeECP/EC Family Data Sheet |
| LFECP15E-5F900I | 12-Bit 66 kSPS ADC Ser. Out, Pgrmable MSB/LSB First, Pgrmable Power Down/Output Data Length, 11 Ch. 20-PDIP |
| LFECP15E-5Q208I | LatticeECP/EC Family Data Sheet |
| LFECP15E-5T100C | Enhanced Product 12-Bit Analog-To-Digital Converter W/ Serial Control And 11 Analog Input 20-SSOP -55 to 125 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LFECP15E-5F484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP15E-5F672C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP15E-5F672I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP15E-5F900C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP15E-5F900I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
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