參數(shù)資料
型號(hào)： LFEC20E-5F672C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 83/163頁
文件大?。?/td> 0K
描述： IC FPGA 19.7KLUTS 400I/O 672-BGA
標(biāo)準(zhǔn)包裝： 40
系列： EC
邏輯元件/單元數(shù)： 19700
RAM 位總計(jì)： 434176
輸入/輸出數(shù)： 400
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 672-BBGA
供應(yīng)商設(shè)備封裝： 672-FPBGA（27x27）
其它名稱： 220-1288
LFEC20E-5F672C-ND
2-23
Architecture
LatticeECP/EC Family Data Sheet
Input Register Block
The input register block contains delay elements and registers that can be used to condition signals before they are
passed to the device core. Figure 2-26 shows the diagram of the input register block.
Input signals are fed from the sysI/O buffer to the input register block (as signal DI). If desired the input signal can
bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and
in selected blocks the input to the DQS delay block. If one of the bypass options is not chosen, the signal first
passes through an optional delay block. This delay, if selected, reduces input-register hold-time requirement when
using a global clock.
The input block allows two modes of operation. In the single data rate (SDR) the data is registered, by one of the
registers in the single data rate sync register block, with the system clock. In the DDR Mode two registers are used
to sample the data on the positive and negative edges of the DQS signal creating two data streams, D0 and D2.
These two data streams are synchronized with the system clock before entering the core. Further discussion on
this topic is in the DDR Memory section of this data sheet.
Figure 2-27 shows the input register waveforms for DDR operation and Figure 2-28 shows the design tool primi-
tives. The SDR/SYNC registers have reset and clock enable available.
The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-
quate timing when data is transferred from the DQS to system clock domain. For further discussion on this topic,
see the DDR Memory section of this data sheet.
Figure 2-26. Input Register Diagram
D
Q
D
Q
D
Q
D-Type
Fixed Delay
To Routing
DI
(From sysIO
Buffer)
DQS Delayed
(From DQS
Bus)
CLK0
(From Routing)
DDRCLKPOL
(From DDR
Polarity Control Bus)
INCK
INDD
Delay Block
DDR Registers
D-Type
D
Q
D
Q
D-Type
/LATCH
D-Type
IPOS0
IPOS1
SDR & Sync
Registers
D0
D2
D1
相關(guān)PDF資料
PDF描述
RBC05DRTN CONN EDGECARD 10POS DIP .100 SLD
LFEC20E-5F484C IC FPGA 19.7KLUTS 360I/O 484-BGA
A562K20X7RL5UAA CAP CER 5600PF 500V X7R AXIAL
T491X106M050AT CAP TANT 10UF 50V 20% 2917
TPSD227M006R0125 CAP TANT 220UF 6.3V 20% 2917
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFEC20E-5F672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC20E-5F900C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC20E-5F900I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC20E-5FN256C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC20E-5FN256I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*